UMC 40nm LP with power gating & peri-HVT 1PRF
UMC 40nm LP with power gating & peri-HVT 1PRF
- UMC
- 40nm
- LP
Embedded memory IP cores are fundamental components in modern SoC and ASIC designs, providing fast and efficient on-chip data storage for processors, accelerators, and peripherals.
These IP cores encompass a broad range of volatile and non-volatile memory technologies, including SRAM for high-speed data storage, ROM for fixed program and boot code storage, register files for processor and accelerator architectures, as well as EEPROM, eFuse/OTP, and MTP (Multiple-Time Programmable) memories for configuration data, security credentials, device calibration, and permanent system information.
This catalog allows you to compare embedded memory IP cores from leading vendors based on density, access time, power consumption, and process node compatibility.
Whether you are designing high-performance processors, AI accelerators, automotive systems, or IoT devices, you can find the right embedded memory IP for your design.
UMC 40nm LP with power gating & peri-HVT 1PRF
UMC 40nm LP with power gating & peri-HVT 1PRF
UMC 40nm Low Power Process PG SP-SRAM with Row redundancy for 213 bit cell
UMC 40nm Low Power Process PG SP-SRAM with Row redundancy for 213 bit cell
40LP PG SP-SRAM LVT Peripheral with Row redundancy for 213 cell
40LP PG SP-SRAM LVT Peripheral with Row redundancy for 213 cell
UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-LVT
UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-LVT
UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-HVT
UMC 40nm LP Logic Process ULL Single Port SRAM Memory Compiler using 213 bit-cell with peri-HVT
UMC 40nm Low Power Process Single-Port SRAM 213cell with power gating
UMC 40nm Low Power Process Single-Port SRAM 213cell with power gating
UMC 40nm Low Power Process SP-SRAM memory compiler with row redundancy and 213 bit cell
UMC 40nm Low Power Process SP-SRAM memory compiler with row redundancy and 213 bit cell
UMC 55nm eHV Process Single Port SRAM with row redundancy for 277cell
UMC 55nm eHV Process Single Port SRAM with row redundancy for 277cell
UMC 55nm eHV Process Single Port SRAM Memory Compiler with Peripheral H/LVT using 277 bit-cell
UMC 55nm eHV Process Single Port SRAM Memory Compiler with Peripheral H/LVT using 277 bit-cell
UMC 55nm uLP LowK Logic Process One Port Register File with forward biased and UHVT periphery
UMC 55nm uLP LowK Logic Process One Port Register File with forward biased and UHVT periphery
UMC 55nm uLP LowK Logic Process One Port Register File with well bias & periphery HVT
UMC 55nm uLP LowK Logic Process One Port Register File with well bias & periphery HVT
UMC 55nm ULP process PG-One Port Register File for periphery HVT
UMC 55nm ULP process PG-One Port Register File for periphery HVT
UMC 55nm ULP process ROM compiler with HVT peripheral
UMC 55nm ULP process ROM compiler with HVT peripheral
UMC 55nm ULP Low-K process One Port Register File for periphery HVT
UMC 55nm ULP Low-K process One Port Register File for periphery HVT
UMC 55nm LP process with PG Dual port SRAM compiler
UMC 55nm LP process with PG Dual port SRAM compiler
UMC 55nm Low-K/Low-Power Logic process synchronous ultra-high-speed single-port SRAM compiler.
UMC 55nm Low-K/Low-Power Logic process synchronous ultra-high-speed single-port SRAM compiler.
55ULP-SST 1P-RF with forward biased and UHVT periphery
55ULP-SST 1P-RF with forward biased and UHVT periphery
55ULP-SST 1P-RF with forward biased and HVT periphery
55ULP-SST 1P-RF with forward biased and HVT periphery
UMC 55nm embedded flash and embedded e2prom ultra low power splite-gate synchronous via1 rom complier with well bias
UMC 55nm embedded flash and embedded e2prom ultra low power split-gate via 1 ROM compiler with well bias