UMC 0.11um eFlash LL process ULL High Density Single-Port SRAM
UMC 0.11um eFlash LL process ULL High Density Single-Port SRAM
- UMC
- 110nm
- LL
Embedded memory IP cores are fundamental components in modern SoC and ASIC designs, providing fast and efficient on-chip data storage for processors, accelerators, and peripherals.
These IP cores encompass a broad range of volatile and non-volatile memory technologies, including SRAM for high-speed data storage, ROM for fixed program and boot code storage, register files for processor and accelerator architectures, as well as EEPROM, eFuse/OTP, and MTP (Multiple-Time Programmable) memories for configuration data, security credentials, device calibration, and permanent system information.
This catalog allows you to compare embedded memory IP cores from leading vendors based on density, access time, power consumption, and process node compatibility.
Whether you are designing high-performance processors, AI accelerators, automotive systems, or IoT devices, you can find the right embedded memory IP for your design.
UMC 0.11um eFlash LL process ULL High Density Single-Port SRAM
UMC 0.11um eFlash LL process ULL High Density Single-Port SRAM
UMC 0.11um BCD High Voltage Process Synchronous Via1 Programmable ROM Compiler
UMC 0.11um BCD High Voltage Process Synchronous Via1 Programmable ROM Compiler
UMC 0.11um BCD process;Single-Port SRAM compiler
UMC 0.11um BCD process;Single-Port SRAM compiler
110nm BCD process Synchronous High-Density Single-Port SRAM Compiler
110nm BCD process Synchronous High-Density Single-Port SRAM Compiler
28nm HPM 1PRF with peri -LVT
UMC 28nm HPC process PG-2PRF with LVT and Bank 2
UMC 28nm HPC process PG-2PRF with LVT and Bank 2
UMC 28nm HPC process 2PRF with LVT and Bank 2
UMC 28nm HPC process 2PRF with LVT and Bank 2
UMC 28nm HPC process PG Two Port Register File with peri-LVT
UMC 28nm HPC process PG Two Port Register File with peri-LVT
UMC 28nm HPC process PG-2PRF with HVT Bank4
UMC 28nm HPC process PG-2PRF with HVT Bank4
UMC 28nm HPC process 2PRF, HVT & Bank2
UMC 28nm HPC process 2PRF, HVT & Bank2
UMC 28nm HPC process PG Two Port Register File with peri-HVT
UMC 28nm HPC process PG Two Port Register File with peri-HVT
UMC 28nm HPC process PG-2PRF with Bank4
UMC 28nm HPC process PG-2PRF with Bank4
UMC 28nm HPC process 2PRF with Bank2 & power gating
UMC 28nm HPC process 2PRF with Bank2 & power gating
UMC 28nm HPC process PG Two Port Register File
UMC 28nm HPC process PG Two Port Register File
UMC 28nm HPC Logic process PG One Port Register File with LVT
UMC 28nm HPC Logic process PG One Port Register File with LVT
UMC 28nm HPC Logic process PG-One Port Register File with HVT
UMC 28nm HPC Logic process PG-One Port Register File with HVT
UMC 28nm HPC Logic process PG One Port Register File
UMC 28nm HPC Logic process PG One Port Register File
UMC 28HPC process standard synchronous high density dual port SRAM memory compiler.
UMC 28HPC process standard synchronous high density dual port SRAM memory compiler.
UMC 28nm HPC process standard synchronous high density dual port SRAM memory compiler.
UMC 28nm HPC process standard synchronous high density dual port SRAM memory compiler.
UMC 28HPC process 1PRF compiler with LVT peripheral
UMC 28HPC process 1PRF compiler with LVT peripheral