Vendor: SmartDV Technologies Category: SD / eMMC Controller

eMMC Verification IP

eMMC Verification IP is an solution in the market for the verification of eMMC implementations.

Overview

eMMC Verification IP is an advanced solution in the market for the verification of eMMC implementations. It is adherent with eMMC standard JESD84-A441, JESD84-B45, JESD84-B50, JESD84-B51, JESD84-B51A & eMMC 5.2(Draft). It can generate all command types. The eMMC VIP monitor acts as powerful protocol-checker, fully compliant with eMMC JESD84-B51 specification.

eMMC JESD84-A441, JESD84-B45, JESD84-B50, JESD84-B51, JESD84-B51A and eMMC 5.2(Draft) includes extensive test suite covering most of the possible scenarios and eMMC conformance norms. eMMC JESD84-A441, JESD84-B45, JESD84-B50, JESD84-B51, JESD84-B51A & eMMC 5.2(Draft) VIP can perform all protocol tests as testbench and moreover it allows an easy generation of a very high number of patterns and a set of specified patterns to stress the DUT.

eMMC Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

eMMC Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Supports eMMC standard JESD84-A441, JESD84-B45, JESD84-B50, JESD84-B51 and JESD84-B51A specification.
  • Supports stream transfer operations.
  • Supports three different data width bus modes
    • 1-bit(default)
    • 4-bit
    • 8-bit
  • Supports boot operation mode with simple boot sequence method.
  • Supports alternative boot operation mode.
  • Supports higher than 2GB of density of memories.
  • Supports hardware reset signal.
  • Supports high speed boot operation.
  • Supports command queuing.
  • Supports enhanced strobe.
  • Supports extended security protocols commands.
  • Supports production state awareness.
  • Supports secure write protect mode.
  • Supports Replay Protected Memory Block(RPMB) functionality.
  • Supports Single byte, single block, multiple block (finite and infinite) transfers and MMC stream transfer operations.
  • Supports send tuning block(CMD21) command.
  • Supports HS200 and HS400 Mode.
  • Supports data protection mechanism like password, permanent ,power-on and temporary.
  • Supports data removable mechanism.
  • Supports packed commands.
  • Supports high voltage & dual voltage.
  • Supports single data rate & dual data rate.
  • Supports write protection features for the boot and user areas, which may be permanent, power-on or temporary.
  • Tracking of transmit and receive counters.
  • Supports bus accurate timing.
  • Detects and reports the following errors.
    • Out of range error
    • Address misalign error
    • CRC error
    • Switch error
    • Illegal command error
    • Block length error
    • Lock-unlock failed error
    • Erase sequence error
    • Direction bit error
    • Stuff bit error
    • Erase param error
    • Reserved bit error
    • WP violation error
    • CSD/CID over write error
  • Protocol Checker fully compliant with eMMC JESD84-A441, JESD84-B45, JESD84-B50, JESD84-B51 and JESD84-B51A Specification.
  • Functional coverage for complete JESD84-A441, JESD84-B45, JESD84-B50, JESD84-B51 and JESD84-B51A.
  • Supports constraints randomization.
  • eMMC Verification IP comes with complete testsuite to test every feature of JESD84-A441, JESD84-B45, JESD84-B50, JESD84-B51 and JESD84-B51A.
  • Configurable as agent (frame generator) or monitor.
  • Status counters for various events on bus.
  • Monitors, detects and notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.

Block Diagram

Benefits

  • Faster testbench development and more complete verification of eMMC designs.
  • Simplifies results analysis.
  • Easy to use command interface simplifies testbench control and configuration of slave and host.
  • Runs in every major simulation environment.

What’s Included?

  • Complete regression suite containing all the eMMC testcases.
  • Examples showing how to connect various components, and usage of Host, Slave and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation contains User's Guide and Release notes.

Files

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
eMMC VIP
Vendor
SmartDV Technologies

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.

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Frequently asked questions about SD / eMMC Controller IP cores

What is eMMC Verification IP?

eMMC Verification IP is a SD / eMMC Controller IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this SD / eMMC Controller?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SD / eMMC Controller IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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