Lowest Power and Cost End Point AI Accelerator
The NeuroMosaic Processor (NMP) family is shattering the barriers to deploying ML by delivering a general-purpose architecture an…
Overview
The NeuroMosaic Processor (NMP) family is shattering the barriers to deploying ML by delivering a general-purpose architecture and simple programmer’s model to enable virtually any class of neural network architecture and use case.
Our unique differentiation starts with the ability to simultaneously execute multiple AI/ML models significantly expanding the realm of capability over existing approaches. This game-changing advantage is provided by the co-developed NeuroMosAIc Studio software’s ability to dynamically allocate HW resources to match the target workload resulting in highly optimized, low-power execution. The designer may also select the optional on-device training acceleration extension enabling iterative learning post-deployment. This key capability cuts the cord to cloud dependence while elevating the accuracy, efficiency, customization, and personalization without reliance on costly model retraining and deployment, thereby extending device lifecycles.
Key features
- Up to 1 TOPS
- Up to 1 MB Local Memory
- RISC-V/Arm Cortex-M 32-bit CPU
- 3 x AXI4, 128b (Host, CPU & Data)
Block Diagram
Benefits
- The NMP-350 extends the low power leadership of the NeuroMosAIc Processor family delivering 60% higher performance efficiency while maintaining concurrent multimodal inferencing matched to modern sensors and embedded systems. Architecture changes include doubling the core count per tile enabling up to 1 TOPS while improving utilization and lowering area by 25%.
- An upgraded RISC-V controller delivers 4x initialization and post-processing performance with the option of swapping with an Arm Cortex-M. Activation function support is expanded to align with state-of-the-art neural network architectures.
- Four MAC unit configurations enable drop-in compatibility with area-constrained systems from sensors and MCUs to dedicated functions within complex SoCs.
Applications
- Driver Authentication, Digital Mirrors, and Personalization
- Predictive Maintenance
- Machine Automation
- Health Monitoring
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Provider
Learn more about Edge AI Accelerator IP core
Using edge AI processors to boost embedded AI performance
The Industry’s First USB4 Device IP Certification Will Speed Innovation and Edge AI Enablement
Accelerating Your Development: Simplify SoC I/O with a Single Multi-Protocol SerDes IP
IoT Was Interesting, But Follow the Money to AI Chips
Designing Energy-Efficient AI Accelerators for Data Centers and the Intelligent Edge
Frequently asked questions about Edge AI Accelerator IP cores
What is Lowest Power and Cost End Point AI Accelerator?
Lowest Power and Cost End Point AI Accelerator is a Edge AI Accelerator IP core from AiM Future, Inc. listed on Semi IP Hub.
How should engineers evaluate this Edge AI Accelerator?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Edge AI Accelerator IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.