Vendor: Synopsys, Inc. Category: CPU

ARC-V RPX Series Functional Safety Processor IP

The ARC-V™ RPX-110 series functional safety (FS) processors, which include the RPX-110-FS, RPX-115-FS, RPX-110V-FS, and RPX-115V-…

Contact Provider Request Datasheet

Overview

The ARC-V™ RPX-110 series functional safety (FS) processors, which include the RPX-110-FS, RPX-115-FS, RPX-110V-FS, and RPX-115V-FS processors simplify development of high-performance safety-critical applications and accelerate ISO 26262 certification for automotive system-on-chips (SoCs). The Automotive Safety Integrity Level (ASIL) D compliant processors feature a pre-verified dual-core lockstep implementation including an integrated safety monitor. Additionally, they offer the flexibility to operate in an independent “hybrid” mode for ASIL B or non-automotive applications that demand higher performance from the same design.

The ARC-V RPX-110 series FS processors are backed by comprehensive safety documentation, including FMEDA reports, and are supported by the ARC-V® MetaWare Toolkit for Safety. This toolkit includes a certified ASIL D compliant compiler, to generate ISO 26262 compliant code.

Key features

  • Dual-issue, 64-bit RISC-V processors for performance efficient host application
  • Configurable solution to support both ASIL B (Single core mode) and ASIL D (Dual core lock step), as defined by ISO 26262
  • Multicore processor versions: up to 16 CPU cores, 12 HW accelerators
    • Per-core configurable in lockstep or hybrid mode: Up to 16x ASIL B or 8x DCLS (ASIL D) cores
  • HW safety features: ECC, integrated user-programmable windowed watchdog timer, E2E for buses/data-path, RAS registers, lockstep and integrated safety monitors
  • RVA22 and optionally RVA23 RISC-V profile compliant
  • Virtualization support through H-extension
  • Up to 64 KB L1 instruction and data cache, optional unified private L2 cache of size 1 MB (shared between main core and shadow core if ASIL D selected), up to 64 MB of L3 shared cluster cache 

Block Diagram

arc-v-rpx-fs block diagram

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
arc-v-rpx-fs
Vendor
Synopsys, Inc.

Provider

Synopsys, Inc.
HQ: USA
Synopsys is a leading provider of high-quality, silicon-proven semiconductor IP solutions for SoC designs. The broad Synopsys IP portfolio includes logic libraries, embedded memories, analog IP, wired and wireless interface IP, security IP, embedded processors and subsystems. To accelerate IP integration, software development, and silicon bring-up, Synopsys’ IP Accelerated initiative provides architecture design expertise, pre-verified and customizable IP subsystems, hardening, and signal/power integrity analysis. Synopsys' extensive investment in IP quality, comprehensive technical support and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market.
Contact Synopsys, Inc.

Learn more about CPU IP core

Announcing Arm AGI CPU: The silicon foundation for the agentic AI cloud era

For the first time in our more than 35-year history, Arm is delivering its own silicon products – extending the Arm Neoverse platform beyond IP and Arm Compute Subsystems (CSS) to give customers greater choice in how they deploy Arm compute – from building custom silicon to integrating platform-level solutions or deploying Arm-designed processors.

Encarsia: Evaluating CPU Fuzzers via Automatic Bug Injection

Hardware fuzzing has recently gained momentum with many discovered bugs in open-source RISC-V CPU designs. Comparing the effectiveness of different hardware fuzzers, however, remains a challenge: each fuzzer optimizes for a different metric and is demonstrated on different CPU designs.

Pie: Pooling CPU Memory for LLM Inference

Pie maintains low computation latency, high throughput, and high elasticity. Our experimental evaluation demonstrates that Pie achieves optimal swapping policy during cache warmup and effectively balances increased memory capacity with negligible impact on computation. With its extended capacity, Pie outperforms vLLM by up to 1.9X in throughput and 2X in latency. Additionally, Pie can reduce GPU memory usage by up to 1.67X while maintaining the same performance. Compared to FlexGen, an offline profiling-based swapping solution, Pie achieves magnitudes lower latency and 9.4X higher throughput.

Frequently asked questions about CPU IP cores

What is ARC-V RPX Series Functional Safety Processor IP?

ARC-V RPX Series Functional Safety Processor IP is a CPU IP core from Synopsys, Inc. listed on Semi IP Hub.

How should engineers evaluate this CPU?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CPU IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP