Vendor: CloudBEAR, LLC Category: CPU

Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex

Maximum performance for running Linux high-end applications.

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Overview

Maximum performance for running Linux high-end applications.
Improved performance compared with Gen#1.

Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex. Designed for a range of applications requiring maximum single thread performance in Linux-capable devices. Improved performance compared with Gen#1.

SMP support

BI-672 has up to 4 cores, each with an L1 caches and a single shared L2 cache implementing fully coherent memory system. Memory coherency between cores allows to use core complex in SMP mode and run common operation system on all cores.

Coherency with peripherals and accelerators

Core complex has special AXI front port connected to coherency controller which provides coherent access for peripherals and accelerators to cached memory ranges simplifies software development and improves performance.

Memory subsystem

Fully non-blocking L1/L2 caches with out-of-order requests processing. Multiple "on-the-fly" requests in L1/L2 caches. L2 cache prefetcher with stride detection of stream and with configurable number of streams. Parallel hardware page table walk for several TLB misses. L1 and L2 TLBs.

Power management

Several power saving modes:

  • After WFI instruction core stops its clock (WFI state)
  • WFI state + core memories in retention state
  • WFI state + core memories in shutdown state
  • Core is power-off
  • L2 cache memories are shutdown (with ¼ granularity)
  • Core complex is power-off

Safe enter/exit from/to these modes:

  • Cache flushes to prevent data loss
  • "Wave"-based memories on/off

Test platform and software package

FPGA testbed for BI series includes complete set of tools to run OS Linux and communicate with it using Ethernet. All necessary software including Linux build, drivers and manuals are provided.

Development Tools

Complete set of RISC-V tools for fast and convenient software development. Compatible with upstream standard development and debug tools: OpenOCD, GCC, GDB, Eclipse. CloudBEAR also provides pre-configured Eclipse-based IDE with prebuilt toolchain and example projects for easy development start.

Key features

  • Configurable instruction set architecture:
    • 64-bit RISC-V with 32 integer registers (I extension)
    • Integer multiplication and division (M extension)
    • Atomic operation support (A extension)
    • Compressed mode for better code density (C extension)
    • IEEE 754-2008 compliant single precision floating point (F extension)
    • IEEE 754-2008 compliant double precision floating point (D extension)
    • Bit manipulation instructions support (B extension)
    • Scalar cryptography instructions support (K extension)
  • RVA22 profile support
  • Decode: up to 3 instructions at cycle
  • Execute: up to 7 instructions at cycle
  • Up to 4 cores in complex
  • Machine, Supervisor and User modes
  • 12 stage out-of-order pipeline
  • Advanced branch predictor
    • L0 micro BTB
    • L1 main BTB
    • BHT
    • RAS
    • Indirect BTB
  • Decoupled predict/fetch reduce bubbles and tolerate I-cache missses
  • Non-blocking branch predictor acts as I-cache prefetcher
  • Sv39 Virtual Memory support
  • 4 to 32 KiB, 2 to 8-way L1 I-cache
  • 4 to 32 KiB, 2 to 8-way L1 D-cache
  • Integrated 128 KiB to 2 MiB L2 Cache
  • L2 stride prefetcher
  • Secondary (L2) TLB
  • Interrupts
    • Advanced Platform Level Interrupt Controller (APLIC)
    • Multi-Core Local Interruptor (CLINT): timer + software interrupts
    • Local interrupt support to provide fast handling
    • Core Local Interrupt Controller (CLIC)
    • Non-Maskable Interrupts (NMIs)
  • ECC memory protection (SEC-DED)
  • Enhanced physical memory protection (Smepmp support)
  • Integrated debug controller including HW breakpoints
  • System bus access
  • Compact JTAG support
  • Trace support
  • Power management support
  • AXI system interface
  • AXI peripheral interface
  • AXI front-port interface for accelerator coherent access
  • Performance
    • 5.99 DMIPS/MHz
    • 8.06 CoreMark/MHz
    • 8.28 SPEC2006 INT/GHz
    • 1.07 SPEC2017 INT/GHz

Block Diagram

BI-672 block diagram

Benefits

  • SMP support and accelerator coherency
    • BI-671 has up to 4 cores, each with an L1 caches and a single shared L2 cache implementing fully coherent memory system. Additional coherency controller provides coherent access for accelerators via AXI front port to cached memory ranges simplifies software development and improves performance.
  • Development Tools
    • Complete set of RISC-V tools for fast and convenient software development. Compatible with upstream standard development and debug tools: OpenOCD, GCC, GDB, Eclipse. CloudBEAR also provides pre-configured Eclipse-based IDE with prebuilt toolchain and example projects for easy development start.
  • 3rd Party Development Tools
    • IAR Embedded Workbench®
    • SEGGER Embedded Studio for RISC-V
    • TRACE32® debugger for RISC-V
  • Compatible Debug Probes
    • BI-671 has integrated Debug module (compliant with RISC-V specification) that allows to use most of standard debug probes. The following debug probes are verified:
      • Digilent HS2
      • Digilent HS3
      • Olimex ARM-USB-TINY
      • Olimex ARM-USB-TINY-H
      • Olimex ARM-USB-OCD
      • Olimex ARM-USB-OCD-H
      • SEGGER J-Link
      • TRACE32® debugger for RISC-V

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
BI-672
Vendor
CloudBEAR, LLC

Provider

CloudBEAR, LLC
HQ: Russia
CloudBEAR company presents on the market a wide range of processor IP of different classes, compatible with RISC-V instruction system: from microcontroller level to high-performance processors with Linux support and the ability to customize for user tasks. The company's products include the BM-series of cores for microcontroller applications, BR-series for embedded systems requiring high real-time performance, and the BI series of Linux-enabled cores.
Contact CloudBEAR, LLC

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Frequently asked questions about CPU IP cores

What is Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex?

Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex is a CPU IP core from CloudBEAR, LLC listed on Semi IP Hub.

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