Compact High-Speed 32-bit CPU Core with DSP

Overview

AndesCore™ D25F is a 32-bit CPU IP core based on AndeStar™ V5 architecture which incorporated RISC-V technology, it is capable of delivering high per-MHz performance and operating at high frequencies, at the same time it is small in gate count. D25F also supports the RISC-V P-extension (draft) DSP/SIMD ISA contributed by Andes, and single-/double-precision floating point instructions. D25F comes with options, including branch prediction for efficient branch execution, Instruction and Data caches, Local Memories for low-latency accesses, ECC for L1 memory soft error protection, and Andes Custom Extension™ (ACE) to add proprietary instructions to accelerate performance/power consumption critical spots.

D25F's 5-stage pipeline is optimized for high operating frequency and high performance. Features also includes PLIC and vectored interrupts for serving various types of system events, AXI 64-bit or AHB 64/32-bit bus, PowerBrake, QuickNap™ and WFI mode for low power and power management, and JTAG debug interface for development support.

Key Features

  • AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
  • DSP/SIMD ISA to boost the performance of digital signal processing
  • Floating point extensions
  • Andes extensions, architected for performance and functionality enhancements
  • Separately licensable Andes Custom Extension™ (ACE) for customized acceleration
  • 32-bit, 5-stage pipeline CPU architecture
  • 16/32-bit mixable instruction format for compacting code density
  • Branch predication to speed up control code
  • Return Address Stack (RAS) to speed up procedure returns
  • Physical Memory Protection (PMP)
  • Flexibly configurable Platform-Level Interrupt Controller (PLIC) for supporting wide range of system event scenarios
  • Enhancement of vectored interrupt handling for real-time performance
  • Advanced CoDense™ technology to reduce program code size

Benefits

  • Performance
    • AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
    • DSP/SIMD ISA to boost the performance of digital signal processing
    • Floating point extensions
    • Andes extensions, architected for performance and functionality enhancements
    • Separately licensable Andes Custom Extension™ (ACE) for customized acceleration
    • 32-bit, 5-stage pipeline CPU architecture
    • 16/32-bit mixable instruction format for compacting code density
    • Branch predication to speed up control code
    • Return Address Stack (RAS) to speed up procedure returns
    • Physical Memory Protection (PMP)
    • Flexibly configurable Platform-Level Interrupt Controller (PLIC) for supporting wide range of system event scenarios
    • Enhancement of vectored interrupt handling for real-time performance
    • Advanced CoDense™ technology to reduce program code size
  • Flexibility
    • Easy arrangement of preemptive interrupts
    • StackSafe™ hardware to help measuring stack size, and detecting runtime overflow/underflow
    • ECC or Parity check on level-one memories for fault protection
    • Several configurations to tradeoff between core size and performance requirements
  • Power Management
    • PowerBrake, QuickNap™ and WFI (Wait For Interrupt) for power management at different occasions

Block Diagram

Compact High-Speed 32-bit CPU Core with DSP Block Diagram

Applications

  • Networking and Communications
  • Advanced Driver-Assistance Systems
  • Video and Image Processing
  • Storage and Media Streaming

Deliverables

  • D25F with AE350 Platform
    • Pre-integrated D25F, PLIC, Debug Module, plus AXI/AHB Platform

Technical Specifications

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Semiconductor IP