ChaCha20-Poly1305 Crypto Engine
The ChaCha20-Poly1305 Crypto Engine is RFC7539 compliant to provide Authenticated Encryption with Associated Data (AEAD) using th…
Overview
The ChaCha20-Poly1305 Crypto Engine is RFC7539 compliant to provide Authenticated Encryption with Associated Data (AEAD) using the ChaCha20 stream cipher combined with the Poly1305 message-authentication code.
Implementation aspects
The ChaCha20-Poly1305 Crypto Engine is available for ASIC and FPGA, with simple interfaces and easy to integrate. It supports a wide range of applications on various technologies. The IP Core can be combined with scatter/gather DMA and AMBA interfaces (AHB/AXI) enabling multi-Gbps throughput in SoC solutions.
This IP Core is also available in the integrated secure element/eSecure IP solution from Secure-IC.
Key features
- ASIC and FPGA
- Fully compliant with RFC7539
- Supports authentication and encryption mode (AEAD)
- Supports stand-alone encryption/decryption (ChaCha20)
- Supports stand-alone authentication (Poly1305)
- Context switching
- AMBA AHB/AXI bridges (with optional scatter/gather DMA)
- Low power features
- Key generation for Poly1305
- ChaCha20
- Dedicated input
- Full synchronous design
Block Diagram
Applications
- TLS/DTLS
- OpenSSH
- IPsec
What’s Included?
- Netlist or RTL
- Scripts for synthesis
- Self-checking TestBench based on FIPS vectors
- Documentation
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Provider
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Frequently asked questions about Symmetric Cryptography IP cores
What is ChaCha20-Poly1305 Crypto Engine?
ChaCha20-Poly1305 Crypto Engine is a Symmetric Crypto IP core from Secure-IC listed on Semi IP Hub.
How should engineers evaluate this Symmetric Crypto?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Symmetric Crypto IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.