Vendor: Noesis Technologies Category: Symmetric Crypto

XTS mode AES Processor

The ntAES_XTS IP Core is fully compliant with AES-XTS algorithm standardized at NIST SP800-38E and IEEE 1619-2007 recommendations…

TSMC 180nm BCDG2 Silicon Proven View all specifications

Overview

The ntAES_XTS IP Core is fully compliant with AES-XTS algorithm standardized at NIST SP800-38E and IEEE 1619-2007 recommendations targeting disk encryption applications at sector (data unit) addressable level. It is also known as a tweakable block cipher where the encryption process is controlled by the tweak a 128-bit value that is generated from the actual logical position of the data unit on the disk. This way identical data units stored at different places will result in different encrypted data thus addressing copy-and-paste attacks. Each data unit size is at least 128-bits. In addition each data unit size can be either an integral or non-integral number of 128-bit blocks. In case where the data unit size is not divisible with 128 then the ciphertext stealing procedure is used to enable correct encryption of the last block. Due to its highly parameterized and scalable architecture the users can trade off logic resources and performance in order to achieve optimum match with their application requirement. The implementation is low on latency, high speed with a simple interface for easy integration in SoC applications.

Key features

  • Supports high throughput AES XTS mode for data storage applications.
  • Compliant with IEEE 1619-2007and NIST SP800-38E recommendations.
  • Supports 128-bit data-path width.
  • Supports 128 bit (XTS-256 mode) or 256-bit (XTS-512 mode) key sizes.
  • Supports cipher stealing mode.
  • Can be configured either as an encryptor or decryptor mode of operation.
  • Provides a throughput rate of 16 Gbps at 125 MHz clock rate.
  • Simple parallel user interface.
  • Scalable architecture for optimal area/performance trade off.
  • Fully synchronous design, using single clock.
  • Portable to any ASIC or FPGA technology for a variety of applications.

Block Diagram

Applications

  • Single SATA 2.0 Hard Disk Drives (up to 3 Gbps throughput rate)
  • Single SATA 3.0 SSD (up to 6 Gbps throughput rate)
  • USB 3.0 compliant storage
  • Encrypted disk drives
  • SSDs for server arrays (up to 64 Gbps typical throughput rate)
  • Encrypted memory sticks

What’s Included?

  • Fully commented synthesizable VHDL or Verilog source code or FPGA netlist.
  • VHDL or Verilog test benches and example configuration files.
  • Comprehensive technical documentation.
  • Technical support.

Files

Note: some files may require an NDA depending on provider policy.

Silicon Options

Foundry Node Process Maturity
TSMC 180nm BCDG2 Silicon Proven

Specifications

Identity

Part Number
ntAES_XTS
Vendor
Noesis Technologies

Provider

Noesis Technologies
HQ: Greece
Noesis Technologies specializes in design,development and marketing of high quality, cost effective communication IP cores and provides expert ASIC/FPGA design services in telecom DSP area. Our solutions are key components to the most sophisticated telecom systems. Backed-up by our leading-edge expertise on forward error correction, encryption and networking technology as well as on DSP algorithm development we provide robust solutions that are used to improve data quality, increase bandwidth or reduce the overall system cost of end-application.

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Frequently asked questions about Symmetric Cryptography IP cores

What is XTS mode AES Processor?

XTS mode AES Processor is a Symmetric Crypto IP core from Noesis Technologies listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.

How should engineers evaluate this Symmetric Crypto?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Symmetric Crypto IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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