Vendor:
CAST
Category:
Protocol Bridge
AXI5 to/from AXI4 Bridge
The AXI-BRG enables communication between an AXI5 interface and an AXI4 interface.
Overview
The AXI-BRG enables communication between an AXI5 interface and an AXI4 interface. The core is designed for minimal latency and area, with its main functions including calculation of check signals from the AXI4 interface and parity checking of signals sent by the AXI5 interface.
The bridge also adds WAKEUP and USER inputs/outputs and offers configuration options to suit different applications. The core provides different error handling options for each signal, including the option to either terminate or propagate the transmission upon error detection.
The AXI-BRG implements a set of maskable interrupt lines for each AXI parity signal independently. The bridges also support both AXI and AXI-Lite protocols through synthesis configuration.
The core includes two bridges: a 4-to-5 bridge that connects an AXI4 Master with an AXI5 Subordinate, and a 5-to-4 bridge that connects an AXI5 Master with an AXI4 Subordinate.
Key features
- Calculation of parity check signals to be sent to the AXI5 interface.
- Parity checking for check signals sent from the AXI5 interface.
- Addition of WAKEUP and channel USER signal inputs/outputs.
- Registered signals on the AXI5 interface.
- Support for both AXI and AXI-Lite through synthesis configuration.
- Bus width options:
- 2N data bits, where 2 < N < 11.
- Configurable address width.
- Configurable number of user bits.
- Parity error output line per AXI signal.
- Configurable error behavior per AXI signal through mode input:
- Terminate transfer and disable core.
- Continue transfer after error reporting.
- Maskable interrupt lines for parity errors per AXI signal.
Block Diagram
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Applications
The AXI-BRG is used when two AXI interfaces of different versions need to communicate.
What’s Included?
Deliverables
The core is available in synthesizable HDL (Verilog) and includes everything required for successful implementation. Its deliverables include:
- Complete test environment.
- Simulation and synthesis script.
- Comprehensive user documentation.
Support
The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.
Specifications
Identity
Part Number
AXI-BRG
Vendor
CAST
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about Protocol Bridge IP cores
What is AXI5 to/from AXI4 Bridge?
AXI5 to/from AXI4 Bridge is a Protocol Bridge IP core from CAST listed on Semi IP Hub.
How should engineers evaluate this Protocol Bridge?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Protocol Bridge IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.