Input 2.0V-3.6V, VBG=1.2V Band-gap, UMC 55nm eflash LP/RVT Logic Process
Input 2.0V-3.6V, VBG=1.2V Band-gap, UMC 55nm eflash LP/RVT Logic Process
- UMC
- 55nm
Analog and Mixed-Signal IP cores are essential building blocks in modern SoC and ASIC designs, enabling seamless interaction between analog signals and digital processing.
These IP cores are widely used for data conversion (ADC, DAC), clock generation (PLL, oscillators), power management, and sensors & monitors such PVT monitors.
This catalog allows you to compare analog and mixed-signal IP cores from leading vendors by performance, power consumption, process node compatibility, and application domain.
Whether you are designing for wireless communication, automotive systems, consumer electronics, or industrial IoT, you can find the most suitable IP solutions for your requirements.
Input 2.0V-3.6V, VBG=1.2V Band-gap, UMC 55nm eflash LP/RVT Logic Process
Input 2.0V-3.6V, VBG=1.2V Band-gap, UMC 55nm eflash LP/RVT Logic Process
Input 2.5V, VBG=1.23V BandGap; UMC 40nm LP/RVT LowK Logic Process_x005F_x000D_
Input 2.5V, VBG=1.23V BandGap; UMC 40nm LP/RVT LowK Logic Process
Power input 3.3V, VBG=1.204V Band-gap, UMC 55nm eFlash process
Power input 3.3V, VBG=1.204V Band-gap, UMC 55nm eFlash process
FXAFE030HH0L is an Analog Front End IP for image processing applications.
OFDM Analog Front End(AFE) , UMC 55nm LP Low-K Logic Process
OFDM Analog Front End(AFE) , UMC 55nm LP Low-K Logic Process
OFDM Analog Front End(AFE) , UMC 55nm LP Low-K Logic Process
OFDM Analog Front End(AFE) , UMC 55nm LP Low-K Logic Process
OFDM AFE using UMC 55nm eFlash Process
OFDM AFE using UMC 55nm eFlash Process
Analog Front End IP for CMOS image processing applications
FXAFE010HF0A is an Analog Front End IP for CMOS image processing applications.
UMC 40nm high performance mono audio codec with highly integrated analog functionality system
UMC 40nm high performance mono audio codec with integrated analog functionality system
UMC 28nm high performance stereo audio codec with highly integrated analog functionality system
UMC 28nm high performance stereo audio codec with integrated analog functionality system
a 10-bit 1-MSPS 11-to-1 SAR-ADC with 11-channel GPIO integrated based on UMC 55nm eFlash process
a 10-bit 1-MSPS 11-to-1 SAR-ADC with 11-channel GPIO integrated based on UMC 55nm eFlash process
a 12-bit 1MSPS SAR-ADC on UMC 40nm LP, with 10-channel GPIO integrated
a 12-bit 1MSPS SAR-ADC on UMC 40nm LP, with 10-channel GPIO integrated
0.9V/1.8V 9Bits 125MSPS Pipelined ADC; UMC 28nm HPC+, LowK, Logic Process
0.9V/1.8V 9Bits 125MSPS Pipelined ADC; UMC 28nm HPC+, LowK, Logic Process
125M 9bit 2.5bit pipeline share-OP ADC for 10/100/1000 Ethernet DPHY use; UMC 28nm HPC/Low-K process
A 12bit 2Msps low power and large voltage range SAR-ADC based on UMC 55nm eflash process
A 12bit 2Msps low power and large voltage range SAR-ADC based on UMC 55nm eflash process
Low power 12bit 4Msps SAR ADC with UMC 55nm EFLASH Process
Low power 12bit 4Msps SAR ADC with UMC 55nm EFLASH Process
10 bit 1MSPS single-end SAR A/D Converter; UMC 28nm HPC process
10 bit 1MSPS single-end SAR A/D Converter; UMC 28nm HPC process
10 bit 1MSPS/200KSPS single-end SAR A/D Converter; UMC 28nm HPC process
10 bit 1MSPS/200KSPS single-end SAR A/D Converter; UMC 28nm HPC process
12Bit 1Msps SAR-ADC based on UMC 55nm uLP process
12Bit 1Msps SAR-ADC based on UMC 55nm uLP process
12Bit 1Msps SAR-ADC based on UMC 55nm uLP eflash process (GPIO Function integrated)
12Bit 1Msps SAR-ADC based on UMC 55nm uLP eflash process (GPIO Function integrated)