The S40LLV25_CODEC_04 integrates: 2-channel 24bit sigma-delta ADC, 2-channel 24bit sigma-delta DAC with headphone driver amplifie…
- Audio Codec
- Available on request
Analog and Mixed-Signal IP cores are essential building blocks in modern SoC and ASIC designs, enabling seamless interaction between analog signals and digital processing.
These IP cores are widely used for data conversion (ADC, DAC), clock generation (PLL, oscillators), power management, and sensors & monitors such PVT monitors.
This catalog allows you to compare analog and mixed-signal IP cores from leading vendors by performance, power consumption, process node compatibility, and application domain.
Whether you are designing for wireless communication, automotive systems, consumer electronics, or industrial IoT, you can find the most suitable IP solutions for your requirements.
The S40LLV25_CODEC_04 integrates: 2-channel 24bit sigma-delta ADC, 2-channel 24bit sigma-delta DAC with headphone driver amplifie…
The GF40LPV25_CODEC_04 integrates: 2-channel 24-bit sigma-delta ADC, 2-channel 24-bit sigma-delta DAC with headphone driver ampli…
The S55LLV25_ADC_13 IP is a 2.5V 12Bit pipeline analog to digital converter capable of running at up to 100MHz conversion rate wi…
UMC 28nm Logic and Mixed-Mode Low-K HPC Process True 1.8V High Frequency Oscillator BOAC IO Cell Library
Faraday 1.8V crystal oscillator I/O Cell Library ; UMC 14nm LOGIC_MIXED-FF+ Process
Faraday 1.8V crystal oscillator I/O Cell Library ; UMC 14nm LOGIC_MIXED-FF+ Process
UMC 55nm e-flash Logic Process OSC High IO Library
UMC 55nm e-flash Logic Process OSC High IO Library
UMC 90nm LL/RVT Low-K Logic Process 2.5VOD3.3V Low Frequency OSC pad
UMC 90nm LL/RVT Low-K Logic Process 2.5VOD3.3V Low Frequency OSC pad
UMC 90nm LL/RVT Low-K Logic Process 2.5VOD3.3V Low Frequency OSC BOAC Pad
UMC 90nm LL/RVT Low-K Logic Process 2.5VOD3.3V Low Frequency OSC BOAC Pad
100MHz Reference Clock Single-end to Differential Buffer for PCIE Gen.I; UMC 0.13um HS/FSG LOGIC/MIXEDMODE Enhance Process
100MHz single-ended to differential clock buffer for UMC 40nm LP.
100MHz single-ended to differential clock buffer for UMC 40nm LP.
DLL-based LVDS RX 3.3v/1.0v ; 55nm SP/RVT LowK Logic Process
DLL-based LVDS RX 3.3v/1.0v ; 55nm SP/RVT LowK Logic Process
DLL-based LVDS RX 3.3v/1.0v ; 55nm SP/RVT LowK Logic Process
DLL-based LVDS RX 3.3v/1.0v ; 55nm SP/RVT LowK Logic Process
DLL-based LVDS RX,VCC=3.3V for 11.5MHz ~ 34.6MHz operation frequency, UMC 0.13um HS FSG Logic Process
DLL-based LVDS RX; VCC=3.3 for 20M~135MHz and VCC=2.5 for 20M~100MHz operation freq.
This IP for DDR4, Input 200MHz - 800MHz, output clock_1X 200MHz - 800MHz, output clock_2X 400MHz - 1600MHz, output,frequency synt…
Input 10M-200M Hz, output 20M-400M Hz, frequency synthesizable PLL; UMC 55nm LP/RVT Low-K Logic Process
Input 6~27MHz, Output 62.5~2000MHz PLL, UMC 28nm HPC process.
Input 6~27MHz, Output 62.5~2000MHz PLL, UMC 28nm HPC process.
Input 200MHz~400MHz, output 200MHz~1600MHz frequency synthesizable PLL; UMC 28nm HPC Logic Process
Input 200MHz~400MHz, output 200MHz~1600MHz frequency synthesizable PLL; UMC 28nm HPC Logic Process
Input 25M~440MHz, output 267M-533M, 200M-400M and 160M-320M, frequency synthesizable PLL; UMC 40nm LP/RVT Logic Process
Input 20M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL; UMC 55nm EFLASH RVT LowK Logic Process