Input 25M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL using MIFS C40LP Logic Process
Input 25M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL using MIFS C40LP Logic Process
- Fujitsu
- 40nm
- LP
Analog and Mixed-Signal IP cores are essential building blocks in modern SoC and ASIC designs, enabling seamless interaction between analog signals and digital processing.
These IP cores are widely used for data conversion (ADC, DAC), clock generation (PLL, oscillators), power management, and sensors & monitors such PVT monitors.
This catalog allows you to compare analog and mixed-signal IP cores from leading vendors by performance, power consumption, process node compatibility, and application domain.
Whether you are designing for wireless communication, automotive systems, consumer electronics, or industrial IoT, you can find the most suitable IP solutions for your requirements.
Input 25M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL using MIFS C40LP Logic Process
Input 25M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL using MIFS C40LP Logic Process
Input 20M-66M Hz, output 400M-800M Hz, frequency synthesizable PLL; UMC 55nm EFLASH/EE2PROM ULP RVT LowK Logic Process
1~50V/V low offset PGA for SAR-ADC ; UMC 0.18um Mixed-Mode PROCESS
1~50V/V low offset PGA for SAR-ADC ; UMC 0.18um Mixed-Mode PROCESS
An 8-bit 10MSPS Programmable Gain Amplifier ;UMC 55nm SP-HVT LowK Logic Process
An 8-bit 10MSPS Programmable Gain Amplifier ;UMC 55nm SP-HVT LowK Logic Process
NO External-R ,frequency 30K~60K ,RC Oscillator .
Internal-R, frequency 48MHz/8MHz. Input 1.08V-1.32V; UMC 55nm EFLASH process
Internal-R, frequency 48MHz/8MHz.
Self-contained ring oscillator, frequency 32KHz.
55nm-SP, FPD-Link Receiver, 3.3V/1.0V, 4 data plus 1 clock channel, 16~85MHz, DLL type,
55nm-SP, FPD-Link Receiver, 3.3V/1.0V, 4 data plus 1 clock channel, 16~85MHz, DLL type,
Input 400M-1600MHz, output 400M-1600MHz, all digital slave delay line of FXADDLL340HH0L to generate 25% delay in period of FREF, …
12 bit 1MSPS R-2R DAC; UMC 55nm eFlash process
12 bit 1MSPS R-2R DAC; UMC 55nm eFlash process
12bits 1MHz Voltage output R-2R D/A Converter; UMC 55nm SP-RVT process
12bits 1MHz Voltage output R-2R D/A Converter; UMC 55nm SP-RVT process
10bits 1MHz R-2R D/A Converter with rail to rail voltage output ; UMC 55nm ULP process
10bits 1MHz R-2R D/A Converter with rail to rail voltage output ; UMC 55nm ULP process
10bits 1MHz R-2R D/A Converter with rail to rail voltage output ; UMC 55nm eFlash (SST) process
10bits 1MHz R-2R D/A Converter with rail to rail voltage output ; UMC 55nm eFlash (SST) process
10bit 250MSPS Current-steering Video D/A Converter; UMC 0.11um HS/FSG Logic Process
10bit 250MSPS Current-steering Video D/A Converter; UMC 0.11um HS/FSG Logic Process
10bit 150MSPS 3-ch Video DAC,UMC 28nm HPC process
10bit 150MSPS 3-ch Video DAC,UMC 28nm HPC process
Power input 1.8v, VBG=0.75V Band-gap, UMC 28nm HPC Logic process
Power input 1.8v, VBG=0.75V Band-gap, UMC 28nm HPC Logic process
Input 1.62V-1.98V, VBG=0.3V BandGap ; UMC 28nm process HPC+ Process
Input 1.62V-1.98V, VBG=0.3V BandGap ; UMC 28nm process HPC+ Process
Input 1.62V-1.98V, VBG=0.3V BandGap ; UMC 28nm process HPC Process
Input 1.62V-1.98V, VBG=0.3V BandGap ; UMC 28nm process HPC Process
Input 1.2V, VBG=0.8V BandGap; UMC 65nm LL/RVT LowK Logic Process_x005F_x000D_ _x005F_x000D_
Input 1.2V, VBG=0.8V BandGap; UMC 65nm LL/RVT LowK Logic Process
Input 2.0V-3.6V, VBG=1.2V Band-gap, UMC 55nm LP/RVT Logic Process
Input 2.0V-3.6V, VBG=1.2V Band-gap, UMC 55nm LP/RVT Logic Process