How do you qualify netlist reduction and circuit extraction?

By Mathias Silvant, president and CEO of edXact SA
edadesignline.com (January 04, 2010)

The significant burden of parasitics on the performance of post-layout verification forces design engineers to use additional techniques in order to match the requirements of next generation designs. A real gap appears between layout extraction and circuit simulation when adding layout parasitics into the flow. A review of the existing techniques as well as a merciless way to doubtlessly validate netlist reduction and circuit extraction are presented in this paper.

Moving forward to advanced technology nodes severely endangers circuit design. The International Technology Roadmap for Semiconductors (ITRS) process technology roadmap together with Moore's Law states that the number of transistors over process nodes raises exponentially, doubling approximately every second year. The number of interconnections between all these transistors and the length and complexity of the supply lines is growing at the same pace. Today, when working on design kits in 40nm and below, more parasitics need to be taken into account in order to model effects. Their impact on circuit function and performance is getting predominant: delay of a signal on a line is mainly determined by the interconnection and its physical parameters and not by the active devices any more.

In order to model interconnections, EDA tools use so-called parasitic elements (resistors, capacitors, coupling capacitors, inductors, mutual inductors and others). We call them parasitic, because they have not been designed, but their behaviour needs to be taken into account. They substantially alter the intended circuit behaviour. Moving from one technology node to the next the number of parasitics increases at least at the same pace as the number of devices: A rule of thumb is about 4 parasitics per transistor. A full-chip extraction of an advanced circuit design will therefore contain several hundreds of millions of those parasitic network components.

CAD engineers and EDA vendors seek to improve current methodologies and flows in order to get a hand on the complexity issue in post-layout simulation. They can take advantage of different techniques, which can all be combined: hierarchical accurate spice simulators, multithreaded and multicore simulation tools, selective extraction approaches, and selective back-annotating of parasitics to pre-layout simulation, improved netlist reduction.

To read the full article, click here