3+ ways to design reconfigurable algorithm accelerator in IP block

Related Semiconductor IP

• CAN XL Verification IP
• Rad-Hard GPIO, ODIO & LVDS in SkyWater 90nm
• 1.22V/1uA Reference voltage and current source
• 1.2V SLVS Transceiver in UMC 110nm
• Neuromorphic Processor IP

Related White Papers

• How to manage changing IP in an evolving SoC design
• EDA in the Cloud Will be Key to Rapid Innovative SoC Design
• Low Power Design in SoC Using Arm IP
• Agile Analog's Approach to Analog IP Design and Quality --- Why "Silicon Proven" is NOT What You Think

Latest White Papers

• OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs
• Balancing Power and Performance With Task Dependencies in Multi-Core Systems
• LLM Inference with Codebook-based Q4X Quantization using the Llama.cpp Framework on RISC-V Vector CPUs
• PCIe 5.0: The universal high-speed interconnect for High Bandwidth and Low Latency Applications Design Challenges & Solutions
• Basilisk: A 34 mm2 End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS