Adaptive Body Biasing (ABB)
Adaptive Body Biasing (ABB) is an advanced power and performance optimization technique used in modern semiconductor technologies—especially in FDSOI, advanced CMOS, IoT chips, mobile processors, and automotive electronics. ABB dynamically adjusts a transistor’s threshold voltage (Vt) by applying forward or reverse biasing to the substrate (body), enabling higher performance, lower leakage, and optimized energy efficiency across different workloads and temperature conditions.
Related Articles
Related Products
- Automotive Adaptive Body Biasing Generator - GLOBALFOUNDRIES 22FDX
- Adaptive Body Bias Generator on Samsung 28nm LN28FDS
- Low Power Memory Compiler - 1-Port Register File Compiler - GF 22nm FDX
- Low Power Memory Compiler - Single Port SRAM - GF 22nm FDX
- Single Rail SRAM GLOBALFOUNDRIES 22FDX
See all 7 related products in the Catalog
Related Blogs
Related News
- VeriSilicon Introduces FD-SOI Wireless IP Platform for Diverse IoT and Consumer Electronics Applications
- Enabled on makeChip and powered by Racyics, the SpiNNaker2 chip forms the core of the newly launched SpiNNcould supercomputer!
- Efficient and GlobalFoundries Partner to Enable a New Category of Ultra Energy-Efficient, High-Performance Processors
- Racyics wins new automotive customer for its GF 22FDX Adaptive-Body-Biasing solution
- CSEM and USJC team up to develop an ultra-low-power chip
The Pulse
- How Cache Coherency Simplifies AI Software
- Multiple neuromorphic chips, one grid, no new middleware
- Hardware-managed heterogeneous high-bandwidth memory and flash in LLM inference systems
- LACE: Large Language Model Aided Multi-Agent Framework for Agile RISC-V Instruction Extension
- Beyond Trusted: What the NSA’s New Guidance Means for Hardware Security
- First Benchmarks Revealed for Jalapeño, OpenAI’s Clean-Sheet General Purpose AI Accelerator ASIC
- A scalable, shader-programmable vector graphics GPU core for low-power MCUs
- MIPS Leads Open Standards Development for Physical AI Platforms as RISC-V International Premier Member
- SEALSQ’s Subsidiary IC'Alps Advances QASIC Roadmap for Sovereign, Quantum-Resistant Application-Specific Integrated Circuits
- NVMe 2.4 Update Adds Post-Quantum Security, Power Controls
- Agentrys Raises $24.5 Million to Build Agentic Design Automation for Chipmakers
- Navigating ISO 26262 Part 11: A Guide for Semiconductor Architects
- Achronix Announces Availability of High-Performance JESD204C IP Core for Speedster7t FPGAs
- Embedded Security explained: Digital signatures
- Apple’s processor cadence: A pending stutter-step for improved long-term edge inference?