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This paper presents the performance verification methods that were set up and used for a SoC recently developed at STM. The SoC is a one-chip satellite...
This paper presents the interconnect solution adopted for an HDTV SoC developed in HVD division of STM. The SoC is a one-chip satellite HDTV set-top...
The Arteris NoC Solution was selected for its ability to effectively manage the on-chip communication of large-scale SoC designs in 65- and 45-nanometer...
The purpose of this paper is to evaluate the benefits of an IP-XACT based environment applied to Network-on-Chip design. We show the level of automation...
The inclusion of Elliptic's hardware and software security engines in Synochip's next generation product will offer improved cryptographic capabilities...
Arteris, Inc., the leading provider of Network-on-Chip (NoC) solutions, today announced that Pixelworks, Inc. has selected Arteris’ on-chip interconnect...
Arteris and Synopsys today announced the integration of Synopsys' DesignWare® DDR Protocol Controller IP and the Arteris NoC solution for complex...
Series C2 Funding to Support Prototype Development, Design Verification and Sampling of Removable Chips for Computer, Server and Consumer Electronics...
Esterel EDA Technologies today announced that STMicroelectronics has applied Esterel Studio for the design of new components for the STBus and ST...
Network on Chip (NoC) is a new paradigm for the design of core based System on Chip. It is expected to provide huge computation power due to its...
The trend towards more scalable, plug-and-play type of communication architectures has become apparent as SoCs have built up on complexity. However,...
This paper presents a new NOC switch architecture which we have called CTCNOC (Central caching NOC) to offer an attractive way to reduce the system...
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