Legacy RTL brought into system-level flow
John Wilson, EE Times
(06/26/2006 9:00 AM EDT)
As system-on-chip complexity grows, designers are turning to electronic system-level (ESL) methodologies to create next-generation designs.
Designers might hesitate to use ESL because of legacy RTL intellectual-property libraries that represent thousands of man-years of invested time. But legacy RTL IP can be the basis for new designs that leverage ESL methodologies.
Designers who have tried ESL design recognize that some parts of a design are more conducive to ESL while others are more efficiently implemented using established IP libraries. Typically, ESL is used to create new, differentiated system components; RTL IP is best for the obligatory nondifferentiated parts of the design.
Where do these two methodologies come together? Actually, they are different aspects of a holistic electronic-system design methodology.
ESL does not replace RTL design. Instead, the ESL design flow extends RTL flows into higher levels of abstraction, much as RTL design extends gate-level design.
Platform-based design lets designers automatically integrate ESL modules with existing RTL IP. Platform-based design is made more effective when it uses Spirit XML data books from the Spirit Consortium to describe the IP. These data books include configuration and validation information to help determine the processes that must be executed to integrate the block into a system-on-chip design.
(06/26/2006 9:00 AM EDT)
As system-on-chip complexity grows, designers are turning to electronic system-level (ESL) methodologies to create next-generation designs.
Designers might hesitate to use ESL because of legacy RTL intellectual-property libraries that represent thousands of man-years of invested time. But legacy RTL IP can be the basis for new designs that leverage ESL methodologies.
Designers who have tried ESL design recognize that some parts of a design are more conducive to ESL while others are more efficiently implemented using established IP libraries. Typically, ESL is used to create new, differentiated system components; RTL IP is best for the obligatory nondifferentiated parts of the design.
Where do these two methodologies come together? Actually, they are different aspects of a holistic electronic-system design methodology.
ESL does not replace RTL design. Instead, the ESL design flow extends RTL flows into higher levels of abstraction, much as RTL design extends gate-level design.
Platform-based design lets designers automatically integrate ESL modules with existing RTL IP. Platform-based design is made more effective when it uses Spirit XML data books from the Spirit Consortium to describe the IP. These data books include configuration and validation information to help determine the processes that must be executed to integrate the block into a system-on-chip design.
To read the full article, click here
Related Semiconductor IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
- TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
Related Articles
- Gbit interface forces analog IP into digital flow
- Transactional level as the new design and verification abstraction above RTL
- From Behavioral to RTL Design Flow in SystemC
- How to raise the RTL abstraction level and design conciseness with SystemVerilog - Part 1
Latest Articles
- Hardware-managed heterogeneous high-bandwidth memory and flash in LLM inference systems
- LACE: Large Language Model Aided Multi-Agent Framework for Agile RISC-V Instruction Extension
- A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node
- Automated Estimation of MBIST Area and Test Time in Heterogeneous Memory IPs via Stacked Ensemble Framework
- VIPER: Architecture-Aware Performance Modeling for Processing-in-Memory Design-Space Exploration