Protecting FPGAs from power analysis security vulnerabilities

By Pankaj Rohatgi, Cryptography Research
pldesignline.com (May 18, 2010)

Overview

Recent advances in the size and performance of FPGAs, coupled with advantages in time-to-market, field-reconfigurability and lower up-front costs, make FPGAs ideally suited to a wide range of commercial and defense applications [6]. In addition, FPGAs generality and reconfigurability provide important protections against the introduction of Trojan horses during semiconductor manufacturing process[8]. As a result, FPGA applications increasingly involve highly-sensitive intellectual property and trade-secrets, as well as cryptographic keys and algorithms [7].

For such applications, FPGAs need to achieve a high level of tamper resistance in order to preserve confidential information and ensure system integrity. Systems that utilize FPGAs for cryptography may also need to comply with tamper-resistance security standards, including applicable Common Criteria protection profiles as well as the upcoming U.S. government FIPS 140-3 standard.

Non-invasive attacks, including both simple and differential power analysis (SPA and DPA), must be addressed by all FPGA-based systems that require any significant degree of tamper resistance. Power analysis attacks can be carried out by attackers with modest skill and resources, since power measurements can be collected and analyzed easily. If a design is not adequately protected, secrets such as sensitive data, IP, trade-secrets and cryptographic keys can be extracted, and adversaries could make unauthorized modifications to the device configuration.

This article introduces SPA and DPA, discusses how these vulnerabilities apply to FPGAs, and provides guidance about the types of countermeasures that can be implemented to protect FPGAs against these attacks.

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