Verifying the vendor tools

Verifying the vendor tools
By Richard Goering, EE Times
May 22, 2000 (10:17 a.m. EST)
URL: http://www.eetimes.com/story/OEG20000522S0007

It's a first-of-its-kind verification tool, never before seen by chip designers. It has brand-new technology that defies categorization! And it will solve your toughest functional verification problems, allowing you to reach time-to-market on those multimillion-gate system-on-chip designs.

Sound familiar? It's probably much like a dozen or so articles you've read in EE Times recently. We are indeed seeing new functional verification technology, along with new companies, every week. All of the introductions sound interesting, and many will prove useful-but all will need a lot of time in the field before they begin to fulfill their promise. Verification tools, like the products for which they are used, need verification too.

Just within the past month, we've seen some interesting rollouts. There's startup Avery Design Automa tion ( www.avery-design.com), which claims to have the first testbench automation tool to support Verilog HDL extensions and Verilog-C/C++ distributed simulation. Real Intent, another startup, offers Verix, claimed to be the first "intent-driven" verification tool. It reads your Verilog HDL, deciphers your intent and runs a series of static checks ( www.realintent.com).

U.K. startup Tenison Technology claims to break new ground with a cycle-accurate, Verilog-to-C compiler (www.tenisontech.com). Co-Design Automation has just come out with SystemSim, the first simulator for Co-Design's Superlog language (www.co-design.com). It also claims to be the first multilingual simulator that doesn't depend on programming language interfaces.

And then there's 0-In Design Automation, which has just come out with 0-In Search, portrayed as t he industry's first "semiformal" tool. It mixes formal model checking with simulation to track down difficult corner cases (www.0-in.com).

0-In's experience is instructive, however. In June 1998, it introduced 0-In Check, which inserted checkers in Verilog code. You didn't hear much about 0-In Check afterward. That's because customers found the tool needed much more sophisticated checks to be truly useful and competitive. A greatly enhanced 0-In Check was reintroduced last March.

Not all the new technologies will go through such a two-year hiatus. But all will need shakedown cruises in the real world, and there will be a learning curve for vendors and users. You're not really buying an off-the-shelf product with these new tools-you're partnering.

Those partnerships, however, were needed for every EDA tool in existence. And the rewards for early adopters are great when technology proves useful.