TSMC's Roadmap Full, But Thin
EUV readied for 7, 5nm--but gains decline
5/2/2018 00:01 AM EDT
SANTA CLARA, Calif. — Continuing to move fast in multiple directions at once, TSMC announced it is in volume production with a 7nm process and will have a version using extreme ultraviolet (EUV) lithography ramping early next year. In addition, it gave its first timeline for a 5nm node and announced a half dozen new packaging options.
Meanwhile, the foundry is pushing power consumption and leakage down on more mainstream 22/12nm nodes, advancing a laundry list of specialty processes and rolling out an alphabet soup of embedded memories. At the same time, it is exploring future transistor structures and materials.
Overall, the Taiwanese giant expects to make 12 million wafers this year with R&D and capex spending both on the rise. It has even started production of 16nm FinFET chips in Nanjing, a big first for China.
To read the full article, click here
Related Semiconductor IP
- 12-bit, 400 MSPS SAR ADC - TSMC 12nm FFC
- 3.3V Capable GPIO on TSMC 28nm RF HPC+
- 1.2V Thin Oxide GPIO on TSMC 28nm RF HPC+
- LDO Voltage Regulator, 250 mA, TSMC N3P
- LDO Voltage Regulator, Adjustable 0.45 V to 0.9 V Output, 30 mA, TSMC N3P
Related News
- Artisan Components Furthers Library Roadmap with TSMC 0.13-Micron Agreement
- 1999 roadmap targets new 'performance SoC' category
- Intel and ARM Finalize Architecture Roadmap Licensing Agreement
- Actel Details Next Phase In Space-Qualified FPGA Roadmap; Aggressively Targets Satellite Payload Applications
Latest News
- TSMC September 2026 Revenue Report
- Lattice Collaborates with Arm to Advance Secure, Adaptable AI Data Center Infrastructure
- ZLG Selects CAST CAN XL and TSN IP for Next-Generation Vehicle-Network Development and Test Tools
- Vayavya Labs and Tenstorrent Partner to Accelerate RISC-V Hardware and Software Development Through Virtual Platform Modeling
- RaiderChip’s Edge NPU reaches more than 50 Generative AI Models with the addition of Qwen3.8-27B