Time for Structured ASIC?
By Gabe Moretti, edadesignline.com
August 07, 2007
Introduced a few years ago as a cheaper replacement to FPGA, Structured ASIC looked for a while as a quick success story for fabless semiconductors manufactures. In fact Altera found it necessary to come out with its own line of structured ASIC devices derived from its Stratix FPGA line just to make sure they would not loose designs initially implemented in FPGA to another manufacturer when the customer achieved volume production.
In fact the segment grew much slower than anticipated and a few startups looking for fame and fortune in this market quickly disappeared. But as development costs and design risks increase at leading edge process nodes, designers are looking for any method or tool that will allow them to meet requirements, schedule, and cost targets. And so, structured ASIC are gaining interest as an implementation alternative.
August 07, 2007
Introduced a few years ago as a cheaper replacement to FPGA, Structured ASIC looked for a while as a quick success story for fabless semiconductors manufactures. In fact Altera found it necessary to come out with its own line of structured ASIC devices derived from its Stratix FPGA line just to make sure they would not loose designs initially implemented in FPGA to another manufacturer when the customer achieved volume production.
In fact the segment grew much slower than anticipated and a few startups looking for fame and fortune in this market quickly disappeared. But as development costs and design risks increase at leading edge process nodes, designers are looking for any method or tool that will allow them to meet requirements, schedule, and cost targets. And so, structured ASIC are gaining interest as an implementation alternative.
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