SystemC reference manual running slightly behind schedule
SystemC reference manual running slightly behind schedule
By Peter Clarke, EE Times
March 6, 2002 (4:49 a.m. EST)
URL: http://www.eetimes.com/story/OEG20020301S0076
PARIS The Open SystemC Initiative (OSCI) is expected to announce at the Design Automaton and Test in Europe (Date) conference that it is pushing ahead with production of a language reference manual (LRM) for SystemC. But the LRM may arrive up to one year later than OSCI had originally planned.
SystemC is a C++ class library and modeling platform being developed for design and verification work beyond the scope of today's HDLs. It has backing from a number of EDA vendors, and OSCI is also aiming for eventual IEEE standardization of the language.
OSCI is preparing to announce at this year's Date conference, which begins Monday (March 4), that it has contracted Paul Menchini, of Menchini and Associates, to develop the LRM for delivery later in 2002. However, the OSCI Web site states that the language's LRM was due " late in 2001."
"Ultimately, delay from original plan occurred due to mundane organizational things like ramp up of OSCI finances and from OSCI being everyone's "second job," said Kevin Kranen, director of strategic programs at Synopsys Inc. and president of OSCI. "No one should be disadvantaged by delay as all have had access to the 'gold standard' for SystemC v2.0, the actual reference implementation, since last July."
Delivery of the LRM is expected to be OSCI's first step towards standardization of SystemC by the IEEE. OSCI expects to present the language to the IEEE for standardization within two years.
Related Semiconductor IP
- MIL-STD-1553 Controller IP
- UFS 5.x Device IP
- UCIe 3.x Controller IP
- Ethernet 800G PCS IP
- CHI to UCIe Bridge IP
Related News
- Accellera Announces Relicensing of SystemC Reference Implementation under the Apache 2.0 License
- Philips Semiconductors continues support behind Velocity Rapid Silicon Prototyping development for ARM946[tm] architecture
- Intel offers details behind Pentium 4 performance increase
- Synopsys and Mentor Graphics to Publish Japanese Translation of Industry-Standard Reuse Methodology Manual
Latest News
- StarFive and LECARC Forge Partnership to Co-Develop RISC-V Server CPUs and Seize New Opportunities in the Agentic AI Era
- ASICLAND Selected as SK hynix’s Partner for Next-Gen eSSD Development, Establishing a ‘K-Semiconductor Win-Win’ Model
- onsemi to Acquire Synaptics to Enable the Next Generation of Intelligent Systems for Physical AI
- EdgeAI Licensed Andes Technology CPU IP to Power Next-Generation Edge AI Neuromorphic Solution
- Jim Keller: ‘AI Still Obeys the Old Laws of Compute’