Startup takes dual IP, ESL role
Richard Goering, EE Times
(07/17/2006 9:01 AM EDT)
SANTA CRUZ, Calif. — CebaTech Inc., launched in 2004 by a group of chip designers who had developed high-level compilation technology for their own needs, this week will announce plans to offer both TCP/IP intellectual property (IP) and the C-language compiler that was used to create it.
CebaTech (Eatontown, N.J.) was started by designers who had developed a behavioral Verilog-to-RTL compiler at Sandgate Technologies in 2000. At that time, Tim Sullivan, former general manager of Lucent's optical area networking division, contracted with the Sandgate engineers to build a 1-Gbyte transport offload engine. Sullivan later joined up with three former Sandgate engineers to launch CebaTech, which he heads as president and CEO.
CebaTech today is expected to divulge plans to offer a tool that can compile C-language descriptions in- to synthesizable register-transfer-level code, as well as compile untimed C into cycle-accurate C models. The company claims to support an electronic system-level (ESL) design methodology that allows an entire system-on-chip to be coded in C and to run in a native C software environment where the cycle-accurate model precisely represents the behavior of the generated RTL.
(07/17/2006 9:01 AM EDT)
SANTA CRUZ, Calif. — CebaTech Inc., launched in 2004 by a group of chip designers who had developed high-level compilation technology for their own needs, this week will announce plans to offer both TCP/IP intellectual property (IP) and the C-language compiler that was used to create it.
CebaTech (Eatontown, N.J.) was started by designers who had developed a behavioral Verilog-to-RTL compiler at Sandgate Technologies in 2000. At that time, Tim Sullivan, former general manager of Lucent's optical area networking division, contracted with the Sandgate engineers to build a 1-Gbyte transport offload engine. Sullivan later joined up with three former Sandgate engineers to launch CebaTech, which he heads as president and CEO.
CebaTech today is expected to divulge plans to offer a tool that can compile C-language descriptions in- to synthesizable register-transfer-level code, as well as compile untimed C into cycle-accurate C models. The company claims to support an electronic system-level (ESL) design methodology that allows an entire system-on-chip to be coded in C and to run in a native C software environment where the cycle-accurate model precisely represents the behavior of the generated RTL.
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