Sony Joins FDSOI Club
Junko Yoshida
1/30/2015 05:15 PM EST
The test chip based on the FDSOI process marks a dramatic reduction in power consumption. A Sony engineer, who spoke at the SOI Industry Consortium in Tokyo, told the audience that Sony was able to cut power consumption in its GNSS chip from 10mW to 1mW.
The Japanese company used STMicroelectronics’ 28nm FDSOI design kit, and manufactured its FDSOI samples at ST's fab.
To read the full article, click here
Related Semiconductor IP
- Chiplet Die-to-Die Interconnect IP Solution
- High speed MACsec Engine 100G/200G/400G/800G/1.6T
- Temperature/Voltage sensors
- AMBA Bus Host to eSPI Controller/Target
- AMBA Bus Host to eSPI Controller
Related News
- Sony To Use FD-SOI in Stacked Image Sensors
- Sony-Inside Huami Watch: Is It Time for FD-SOI?
- Three customers, STMicroelectronics, ARM Ltd. and Sony Corp. invest in CoWare
- CoWare to Enter Licensing and Technical Support Agreement with Sony To Speed Chip Design for Sony's Next-Generation AV-IT Products
Latest News
- Alliance for Open Media Releases AV2 Codec, Advancing Next-Generation Open Video Coding
- VeriSilicon Drives Commercial Adoption of AV2 Across Next-Generation Video and Streaming Applications
- Cadence Announces Collaboration with Intel Foundry to Accelerate Intel 14A Process Optimization for HPC and Mobile Designs
- Menta and Presto Engineering Announce Strategic Collaboration to Accelerate Adaptive ASIC Architectures with Embedded FPGA Technology
- MIPI A-PHY To Power Industry’s First Four-Company Automotive SerDes Interoperability Demonstration at AutoSens USA