Sonics releases memory scheduler core

Sonics releases memory scheduler core
By Nicolas Mokhoff, EE Times
March 4, 2002 (3:49 p.m. EST)
URL: http://www.eetimes.com/story/OEG20020304S0059

PARIS — Sonics Inc. introduced a memory scheduler core at the Design Automation and Test in Europe conference here. The intellectual property core will sit between any memory controller based on the Open Core Protocol and the company's SiliconBackplane MicroNetwork IP, a glue for IP cores.

The Open Core Protocol (OCP) is a defined interface between IP cores and on-chip communication subsystems that is promoted by Sonics (Mountain View, Calif.) and other IP vendors.

The MemMax scheduler core provides the initiator and task information necessary to schedule memory transactions in a way that maximizes memory performance, Sonics said. The patent-pending core has demonstrated DRAM access efficiency improvements up to 40 percent greater than traditional fixed-bus approaches, according to Drew Wingard, chief technical officer at Sonics.

"MemMax consolidates the intelligence requir ed to effectively manage data at what is almost always the most congested target on the chip — the shared memory subsystem," he said. An optimized memory subsystem solution would consist of a MemMax scheduler, a conventional DRAM controller with an OCP interface, and DRAM chips, according to Wingard.

MemMax is configurable through a graphical user interface and can support up to eight request threads with three level of services. The core is available immediately; pre-design licensing fees start at $75,000.