Sofics Tapes Out Test Chip on TSMC 4nm Process with Novel ESD IP and Low-Power 1.8V and 3.3V GPIO Solutions

Sofics’ solutions empower IC design with superior power-performance-area and robustness benefits

BELGIUM – October 21, 2025 – Sofics BV, a world leading solution provider specializing in physical layout and design, with a focus on the built-in robustness of integrated circuits that demand superior power, performance, and area (PPA), today announced the successful tape-out of a new test chip on TSMC N4C process. The test chip integrates a suite of next-generation electrostatic discharge (ESD) protection clamps and versatile 1.8V and 3.3V GPIO circuits optimized for high performance, low leakage, and robust operation. Such IP is relevant for emerging demands in mobile, automotive, HPC, and AI applications.

This milestone builds on Sofics’ continued collaboration with TSMC and reinforces Sofics’ commitment to offering proven IP to its fabless semiconductor customers designing on the industry’s most advanced process nodes.

Advanced ESD Solutions for 4nm Innovation

The test chip features a comprehensive set of ESD clamp designs targeting a wide voltage spectrum including 0.75V, 1.2V, 1.8V, 2.5V, and 3.3V. These solutions explore a variety of clamp concepts, optimized for application-specific trade-offs between area, robustness, leakage, and parasitic capacitance. With proven scalability, Sofics’ technology enables silicon designers to balance PPA and robustness without compromise.

New GPIO Architectures and Integrated Voltage Regulators

Sofics also leveraged this test chip to develop critical foundation IP for next-generation general-purpose interfaces:

• A 3.3V-capable overvoltage-tolerant (OVT) GPIO base cell
• A matched voltage regulator to support the internal supplies required by the 3.3V OVT-GPIO
• A low-power regulator supporting TSMC’s 1.8V GPIO interface, delivering intermediate voltage supplies with optimized power efficiency.

These developments reflect Sofics’ holistic approach to I/O and robust co-design, delivering not only interface IP but the associated infrastructure to ensure safe, efficient operation at scale.

“ We’re excited to extend our IP portfolio leveraging TSMC’s N4C platform, supporting customers who demand the best in performance, robustness, and design flexibility. Our collaboration with TSMC through its Open Innovation Platform® (OIP) allows us to deliver silicon-proven solutions aligned with the requirements of advanced SoC and chiplet-based designs.” said  Koen Verhaege, Sofics CEO

A Trusted Design Partner

Sofics has been part of the TSMC OIP IP Alliance since 2010 and has supported many mutual customers with specialty interface design and ESD solutions ever since. Sofics IP is used in billions of devices across wireless, consumer, industrial, automotive, and data center applications. The IP solutions for the TSMC N16FFC, N12FFC, N7, N5, N4C, N3E, and the nanosheet based technology, N2P, are now available for licensing by customers targeting next-generation nodes with demanding ESD, leakage, area, and voltage interface requirements.

About Sofics

Sofics (www.sofics.com) is a leading independent provider of semiconductor IP for on-chip ESD, I/O and reliability solutions. Sofics IP is integrated in more than 5000 tape outs across CMOS, FinFET, BCD and SOI processes.