RISC-V Targets Data Centers, Edge AI, Space
As RVA23 becomes globally adopted RISC-V open architecture reaches server maturity.
By Pablo Valerio, EE Times | June 11, 2026

BOLOGNA, Italy — For years, RISC-V open-standard instruction set architecture worked quietly behind the scenes, mostly appearing in microcontrollers, hard drives, and specialized industrial applications. But at this week’s RISC-V Summit Europe 2026 in Bologna, the message to the global tech community was unequivocal: The architecture has matured and now targets data centers, edge AI, and space exploration markets.
“RISC-V is now,” said Andrea Gallo, CEO of RISC-V International, during his opening keynote address to a full auditorium.
Gallo’s speech showed that RISC-V is close to major commercial growth. According to the SHD Group, RISC-V could reach 33.7% market share across all hardware segments by 2031.
To read the full article, click here
Related Semiconductor IP
- RISC-V Debug & Trace IP
- RISC-V IOPMP IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- 64-bit RISC-V core with in-order single issue pipeline. Tiny Linux-capable processor for IoT applications.
- Multi-core capable RISC-V processor with vector extensions
Related News
- SiFive’s New RISC-V IP Combines Scalar, Vector and Matrix Compute to Accelerate AI from the Far Edge IoT to the Data Center
- SiFive to Power Next-Gen RISC-V AI Data Centers with NVIDIA NVLink™ Fusion
- Altera and Arm Collaborate to Deliver Efficient, Programmable Solutions for AI Data Centers
- Innatera and Akeana collaborate to advance energy-efficient RISC-V compute for edge AI
Latest News
- Kandou AI Selects Baya Systems to Power Its Attack on the AI Memory Wall
- Arteris Expands Partnership with Arm to Accelerate Semiconductor Cybersecurity
- OpenTitan Earl Grey 2 to support CHERI and PQC
- TSMC June 2026 Revenue Report
- Quadric Extends Series C to $46M with Second Close led by World Bank's IFC