Startup Ricursive to Create an End-to-End AI Model for Chip Design
By Sally Ward-Foxton, EE Times | June 10, 2026

Palo Alto, Calif. — Startup Ricursive, founded by the two leads from Google’s famous AlphaChip project, is aiming to develop an end-to-end AI model for chip design. The new AI frontier lab is focused on hardware workload co-optimization, with the first stages of its rollout targeting workload-specific chip design for third parties. The company has raised $335 million, which will largely be spent on GPU compute hours as it trains and tests its model.
In an exclusive interview with EE Times, Ricursive co-founder and CEO Anna Goldie, as well as co-founder and CTO Azalia Mirhoseini, stressed that the startup is not an EDA company, will not compete with EDA companies, and will not utilize standard EDA toolchains.
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