Physical verification tool makes direct mask link
Physical verification tool makes direct mask link
By Michael Santarini, EE Times
October 2, 2001 (3:11 p.m. EST)
URL: http://www.eetimes.com/story/OEG20011002S0082
SAN MATEO, Calif. Mentor Graphics Corp. is developing an option to its Calibre physical verification tool that will allow engineers who create masks with Calibre to bypass using Numerical Technologies' CATS tool and directly send layout information to mask writers. Joseph Sawicki, general manager of the Calibre Business Unit at Mentor, said the direct link to mask writers preserves layout hierarchy and allows mask writers to more efficiently process large designs. Sawicki explained that mask data preparation (MDP) has become a serious bottleneck in the semiconductor industry, because data volumes are increasing to unmanageable sizes. He said that if data is handled incorrectly or flattened too early in the process, as is commonly done with current methods, the volume of IC data can increase by a factor of 10 or more, staggering mask-writing and inspection time. "The option lets you take advantage of all the hierarchical processing Cal ibre does, but now further down in the tapeout cycle," said Sawicki. "The tool outputs to a Mebes machine. That means that all the layer derivations, sizing operations and the like can be done hierarchically, which allows engineers to get rid of week-long run-times." Sawicki said that the tool will allow engineers to bypass using Numerical Technologies' Computer Aided Transcription System (CATS) fracturing tool and all its proprietary formats. The CATS tool takes in GDSII design data and converts it into the data formats needed to drive machines that write, measure and inspect masks and wafers. Sawicki said that the new MDP option is currently in beta and should be available for the mass market by mid 2002.
Related Semiconductor IP
- Mesochronous Bridge for PCIe/CXL
- AI-native GPU
- OpenGMSL Verification IP
- OpenGMSL Leaf IP
- FlexGen Multi-Die Smart Network-on-Chip (NoC) IP
Related News
- UMC Certifies Synopsys IC Validator Physical Verification Tool for 28 nm
- Avatar Integrated Systems Physical Implementation Tool Certified on TSMC 7nm FinFET Process
- OIF Marks 25th Anniversary, Launches New Physical & Link Layer Working Group Electrical Project and Adds 112G VSR Clause to CEI 5.0 IA at Q1 Technical and MA&E Committees Meeting
- Cadence Extends Collaboration with TSMC and Microsoft to Advance Giga-Scale Physical Verification in the Cloud
Latest News
- SignatureIP Unveils MesoLink, a Mesochronous Bridge for PCIe/CXL Validation
- ICTK Partners with Jiran Security to Drive Post-Quantum Cryptography (PQC) Migration
- S2C Named Andes Technology’s 2026 Partner of the Year
- BrainChip Launches AKD1500 PCIe Card For Edge AI Evaluation Everywhere
- TDK-Micronas adopts Aniah’s AI-powered OneCheck® platform to advance automotive semiconductor development