Panel confronts multicore pros and cons
Richard Goering, EE Times
(03/23/2006 8:42 PM EST)
SANTA CLARA, Calif. — Panelists at the Multicore Expo here Wednesday (March 22) generally agreed that multitasking and multiprocessing have bright futures, although they identified some challenges as well. One of those challenges is the difficulty of programming next-generation multicore ICs.
Multithreading, said Michael Uhler, CTO of MIPS Technologies, provides an increase in performance without compromising power. He said the number of cores may be reduced as cores take on more capabilities, including multithreading. That's consistent with MIPS' position in February, when the company rolled out its MPS34K, a "virtual CPU" core that MIPS believes can forestall the need to move to multicore designs for some multimedia and network applications.
Heterogenous or asymmetric multiprocessing (AMP) multicore systems-on-chip (SoCs) are being built because they have lower bill of materials costs, Uhler said. "It wouldn't surprise me to see SMP [symmetric multiprocessing] on the host processor, with the system remaining AMP because of the BOM cost," he said.
(03/23/2006 8:42 PM EST)
SANTA CLARA, Calif. — Panelists at the Multicore Expo here Wednesday (March 22) generally agreed that multitasking and multiprocessing have bright futures, although they identified some challenges as well. One of those challenges is the difficulty of programming next-generation multicore ICs.
Multithreading, said Michael Uhler, CTO of MIPS Technologies, provides an increase in performance without compromising power. He said the number of cores may be reduced as cores take on more capabilities, including multithreading. That's consistent with MIPS' position in February, when the company rolled out its MPS34K, a "virtual CPU" core that MIPS believes can forestall the need to move to multicore designs for some multimedia and network applications.
Heterogenous or asymmetric multiprocessing (AMP) multicore systems-on-chip (SoCs) are being built because they have lower bill of materials costs, Uhler said. "It wouldn't surprise me to see SMP [symmetric multiprocessing] on the host processor, with the system remaining AMP because of the BOM cost," he said.
To read the full article, click here
Related Semiconductor IP
- MIL-STD-1553 Controller IP
- UFS 5.x Device IP
- UCIe 3.x Controller IP
- Ethernet 800G PCS IP
- CHI to UCIe Bridge IP
Related News
- Letter to the editor: IP pros, cons (Jonah Probell)
- NXP CoolFlux BSP's 12-bit computation has pros and cons for low-power baseband
- Taiwan confronts SoC obstacles
- Panel debates value of mixed-signal design tools
Latest News
- StarFive and LECARC Forge Partnership to Co-Develop RISC-V Server CPUs and Seize New Opportunities in the Agentic AI Era
- ASICLAND Selected as SK hynix’s Partner for Next-Gen eSSD Development, Establishing a ‘K-Semiconductor Win-Win’ Model
- onsemi to Acquire Synaptics to Enable the Next Generation of Intelligent Systems for Physical AI
- EdgeAI Licensed Andes Technology CPU IP to Power Next-Generation Edge AI Neuromorphic Solution
- Jim Keller: ‘AI Still Obeys the Old Laws of Compute’