OCP-IP Delivers Even More OSCI TLM 2.0 Compatibility in Advanced SystemC TLM Kit

REDWOOD CITY, Calif. -- January 27, 2010 -- Open Core Protocol International Partnership (OCP-IP) today announced the availability of version 2.2x2.1 of the OCP Modeling Kit. The new version is compatible with OSCI’s TLM 2.0.1, the most recent version of TLM 2. The work by OCP-IP’s System Level Design Working Group significantly increases performance, ease of use and ensures alignment with the OSCI 2.0 standard and is the most advanced TLM-2.0 based, industry-ready kit in existence today. The Kit is free as part of OCP-IP membership entitlement and will save users hundreds of thousands of dollars each year in development, documentation, and training cost which would be required to develop such kits independently.

The new revision continues to leverage OSCI 2.0 for all levels of abstraction and includes TL4 which is equivalent to OSCI's "loosely-timed" (LT) level. TL1 is fully cycle-accurate, including support for clock cycle synchronization and combinatorial paths. TL2 handles intra-burst timing. TL3 and TL4: inter-burst or no timing, equivalent to OSCI’s Base Protocol.

The Kit includes everything needed for immediate use. For a detailed listing of everything included see http://www.ocpip.org/uploads/documents/OCP_TLM_Datasheet.new.pdf.

A fully functional version of the Kit without monitors is also available to non-members, via click through research license agreement from www.ocpip.org.

This Kit was developed by OCP-IP member companies working with Greensocs, Ltd. It interoperates seamlessly with other TLM utilities, such as GreenSocket from GreenSocs.

For the latest information on OCP-IP please see our newsletter at http://www.ocpip.org/newsletters.php

About OCP-IP

Formed in 2001, OCP-IP is a non-profit corporation promoting, supporting and delivering the only openly licensed, core-centric protocol comprehensively fulfilling integration requirements of heterogeneous multicore systems. The Open Core Protocol (OCP) facilitates IP core reusability and reduces design time, risk, and manufacturing costs for all SoC and electronic designs by providing a comprehensive supporting infrastructure. For additional background and membership information, visit www.OCPIP.org.