New IPs From ChipIdea Achieve Mass Production Status
Tagus Park-Porto Salvo-Portugal-November 26, 2003, ChipIdea Microelectronics SA announces that two new IP cores from its vast IP portfolio for embedded SoC applications have successfully achieved Mass Production status 1. CI3157va--10-Bit, 100kHz, 3.3V SAR ADC This IP core was designed for 0.18um CMOS single-poly and can be retargetable into any sub-micron CMOS technology with 2.5V/3V supply.
All biasing circuits are included, with only the need of an external reference voltage to define the full-scale range. This voltage could be derived from the analog supply voltage. A power down capability is included with less than 1uA of standby current. An analog multiplexer is provided to enable selection from 4 inputs. This IP core is suitable for application as a microprocessor peripheric A/D converter. 2. CI8158va - 10-Bit, 1 MHz, 3.3V Current-Steering DAC The CI8158va is a 10-bit auxiliary DAC core cell designed in 0.18um CMOS single-poly and can be retargetable into any sub-micron CMOS technology with 2.5V/3V supply.
This IP core uses a current-steering D/A converter followed by an output voltage-mode buffer. Due to its architecture, the conversion characteristics exhibit excellent linearity. This IP core is ideally suited in low-power applications requiring low resolution and medium speed.
More details about these two cells can be found in www.chipidea.com.
All biasing circuits are included, with only the need of an external reference voltage to define the full-scale range. This voltage could be derived from the analog supply voltage. A power down capability is included with less than 1uA of standby current. An analog multiplexer is provided to enable selection from 4 inputs. This IP core is suitable for application as a microprocessor peripheric A/D converter. 2. CI8158va - 10-Bit, 1 MHz, 3.3V Current-Steering DAC The CI8158va is a 10-bit auxiliary DAC core cell designed in 0.18um CMOS single-poly and can be retargetable into any sub-micron CMOS technology with 2.5V/3V supply.
This IP core uses a current-steering D/A converter followed by an output voltage-mode buffer. Due to its architecture, the conversion characteristics exhibit excellent linearity. This IP core is ideally suited in low-power applications requiring low resolution and medium speed.
More details about these two cells can be found in www.chipidea.com.
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