Mosis offers IBM 90-nm process on MPW
Peter Clarke, EE Times
(05/09/2006 3:13 PM EDT)
MUNICH, Germany
(05/09/2006 3:13 PM EDT)
MUNICH, Germany
â The Mosis integrated circuit fabrication service has begun offering multi-project wafer (MPW) runs on 90-nanometer process technologies from IBM, according to Paul Double, managing director of EDA Solutions Ltd.
The process is the 9SF process, which comes in three variants, low power digital, standard digital and analog and RF, said Double. The first customer submission deadline is Dec. 4, 2006, according to the Mosis website.
To read the full article, click here
Related Semiconductor IP
- MIL-STD-1553 Controller IP
- UFS 5.x Device IP
- UCIe 3.x Controller IP
- Ethernet 800G PCS IP
- CHI to UCIe Bridge IP
Related News
- Dolphin Integration first to achieve 0.84 pA per bit in SpRAM at the 90 nm uLL embedded flash process
- Dolphin Integration announces the availability of the new generation of SpRAM generator at 90 nm and 55 nm eFlash
- Mikron Licenses Cadence Physical Verification System and QRC Extraction Solutions for 90 nm IC Design Flow
- Dolphin Integration announce the availability of the TSMC sponsored sROMet and DpRAM generators at 90 nm LP eFlash
Latest News
- StarFive and LECARC Forge Partnership to Co-Develop RISC-V Server CPUs and Seize New Opportunities in the Agentic AI Era
- ASICLAND Selected as SK hynix’s Partner for Next-Gen eSSD Development, Establishing a ‘K-Semiconductor Win-Win’ Model
- onsemi to Acquire Synaptics to Enable the Next Generation of Intelligent Systems for Physical AI
- EdgeAI Licensed Andes Technology CPU IP to Power Next-Generation Edge AI Neuromorphic Solution
- Jim Keller: ‘AI Still Obeys the Old Laws of Compute’