Mentor package helps verify TI DSPs
By
February 24, 2004 (11:14 a.m. EST)
URL: http://www.eetimes.com/story/OEG20010227S003961
Related Semiconductor IP
- NPU IP
- JPEG XL Encoder
- I2C Master/Slave Controller Core
- NVMe Validation Test Suite
- Hybrid Memory Cube Verification IP
Related News
- TI fires up C64X-based DSPs for 3G wireless run
- Intel's XScale platform takes shot at TI DSPs
- 0-In Design Automation Helps AMD Verify Complex Networking and Processor Chipsets
- Mentor Graphics Announces EZ-VIP Package for Enhanced Testbench Productivity
Latest News
- GF unveils roadmap to deliver the world’s most advanced FD-SOI platform for Physical AI
- GlobalFoundries marks Dresden expansion milestone, announces next-generation platform for Physical AI
- TSMC September 2026 Revenue Report
- Lattice Collaborates with Arm to Advance Secure, Adaptable AI Data Center Infrastructure
- ZLG Selects CAST CAN XL and TSN IP for Next-Generation Vehicle-Network Development and Test Tools