Menta and Presto Engineering Announce Strategic Collaboration to Accelerate Adaptive ASIC Architectures with Embedded FPGA Technology

Partnership combines embedded FPGA innovation with end-to-end ASIC industrialization expertise to enable flexible, future-proof semiconductor solutions

Sophia-Antipolis and Meyreuil, France, June 8, 2026 – Menta, a pioneer and recognized leader in standard-cell-based embedded FPGA (eFPGA) technology, and Presto EngineeringGroup, a global leader in application-specific integrated circuit (ASIC) supply and semiconductor services, today announced a strategic collaboration to simplify and accelerate the development of adaptive semiconductor architectures by combining Menta’s eFPGA technology with Presto Engineering’s ASIC design and industrialization expertise.

The partnership establishes Presto Engineering as a select design partner for Menta, providing unique access to Menta’s eFPGA IP portfolio, specialized integration knowledge and dedicated technical support. Together, the companies will help customers create ASIC and system-on-chip (SoC) solutions that combine ASIC-grade performance and efficiency with post-deployment hardware adaptability. The partnership supports a broader industry shift toward future-proof semiconductor architectures capable of evolving after deployment, without requiring costly full-chip redesigns.

“Menta and Presto Engineering share a common vision around adaptive semiconductor architectures,” said Vincent Markus, CEO of Menta. “As semiconductor systems become increasingly complex and long-lived, customers need solutions that allow hardware to evolve over time. By combining our eFPGA technology with Presto Engineering’s expertise in ASIC implementation and industrialization, we are creating a more seamless path from innovation to production deployment.”

According to Frédéric Valentin, Senior Vice President Sales and Marketing, Presto Engineering, “We are excited to execute this joint agreement with Menta to serve our complementary global customer base and have already collaborated with several companies about upcoming FPGA-to-ASIC transition projects. Most importantly, this partnership will help to strengthen the semiconductor ecosystem with a specialized design and production solution from architecture definition to product deployment.”

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• eFPGA Soft IP

The partnership addresses a major industry challenge: combining ASIC efficiency with FPGA-like adaptability. By integrating eFPGA technology, customers gain the ability to update algorithms after deployment, adapt to changing standards and protocols, reduce costly silicon redesigns, extend product lifecycle and improve security and crypto agility. The collaboration is particularly well suited for applications requiring long lifecycle support and evolving functionality, including:

• AI acceleration and edge AI
• Secure communications and cryptography, including post-quantum security applications
• Aerospace systems
• Industrial automation and embedded systems
• High-performance computing
• Signal processing and networking infrastructure
• Radiation-tolerant and long-lifecycle semiconductor solutions

Through the collaboration, Menta will provide eFPGA IP technology and architecture expertise, flexible hardware acceleration capabilities, foundry- and technology-node-independent standard-cell architectures, training and dedicated technical support. 

Presto Engineering will contribute ASIC architecture, design, and integration services; eFPGA-aware floor planning and optimization; design-for-test, qualification and silicon validation expertise; secure supply chain and lifecycle management; and production industrialization support. 

Initially focused on Europe, the partnership targets global markets across North America and Asia, including customers in aerospace, industrial, communications, medical, and critical infrastructure sectors such as AI, security, and edge computing.

For more information, visit Menta: https://www.menta-efpga.com/solutions-asic-semiconductor-partners or Presto: https://www.presto-eng.com/fpga-to-asic.