HDL Design House Introduces JESD204B PCS IP Core
Belgrade, Serbia – April 23, 2013 - HDL Design House, provider of high performance digital and analog IP cores and SoC design and verification services, has announced the availability of its JESD204B Physical Coding Sublayer (PCS) IP core (HIP 600), which enables transmission and reception of data via a configurable number of lanes in compliance to JEDEC’s JESD204B specification.
The JESD204B PCS IP Core performs frame generation, encoding, and scrambling for data transmission, as well as decoding, frame recovery, intra and inter lane alignment, and descrambling on data reception. It is highly configurable via an APB interface, and supports subclass 0, 1, & 2 data latency handling.
For test purposes, the JESD204B PCS IP offers built-in PRBS generator/verifier pairs, as well as various loopback data path modes.
About HDL DH FlexIP core library
The FlexIP core library includes a broad portfolio of high-quality, silicon proven digital and analog IP cores for SoC designs. The library covers a large number of standards and protocols such as HDMI, DisplayPort, MIPI (DSI, UniPro and CSI, DigRF, BIF), USF, I2S, Serial RapidIO, SPI flash memory controller, PCI Express, SATA, USB 3.0, and others. Apart from the large number of supported protocols and standards, one of the greatest competitive advantage for users of the FlexIP core library is HDL Design House outstanding capabilities in providing integration services, customization of the IP core at customer's request, verification solutions for the given IP core, as well as on site support. For more information on the FlexIP core library, please go to http://www.hdl-dh.com/products.html
About HDL Design House
HDL Design House delivers leading-edge digital and analog design and verification services and products in numerous areas of SoC and complex FPGA designs. The company also develops IP cores and offers back-end services. The company has extensive experience with the ARM CPU architecture, ARM CPU processor interfaces and development or integration of SoC based on ARM CPU. Founded in 2001 and currently employing 60 engineers working in two design centers in Serbia, HDL Design House mission is to deliver high quality products and services, with flexible licensing models, competitive pricing and responsible technical support. The company was awarded ISO 9001:2000 and ISO 27001:2005 certifications in December 2006/2009. For more information, please visit www.hdl-dh.com
Related Semiconductor IP
Related News
- HDL Design House Introduces JESD204B PCS Rx IP Core
- HDL Design House Announces JESD204B PCS Tx IP Core HIP 600
- TES offers PKCS IP Core for System-on-Chip (SoC) Designs
- Fraunhofer IPMS develops new 10G TSN endpoint IP Core for deterministic high-speed Ethernet networks
Latest News
- Brite Semiconductor Releases 28nm High-Performance SAR ADC IP, Driving Upgrades for High-Speed Signal Chain Applications
- Synopsys Updates CXL IP Portfolio for AI-Era Infrastructure
- BrainChip Launches Symphony Community Akida Bundle For IBM’s Workload Management Solution
- StarIC Appoints Dr. Masum Hossain as Chief Technology Officer
- Andes Technology Empowers RISC-V Developers with Its New Streamlined IDE, RVBuilder