Interview: Aart de Geus on AI-driven EDA
By Nitin Dahad, EETimes (March 29, 2023)
At the Synopsys Users Group conference, SNUG 2023, in Santa Clara this week, the company’s chairman and CEO, Aart de Geus, used the keynote speech to talk about the need for AI-driven EDA tools, as Synopsys launched Synopsys.ai, a suite of AI-driven solutions for the design, verification, testing and manufacturing of the most advanced digital and analog chips.
The company said that for the first time, engineers can now use AI at every stage of chip design, from system architecture to design and manufacturing, and access the solutions in the cloud. Renesas, a leader in the automotive space, is already using Synopsys.ai to shave weeks off product development times with enhanced silicon performance and cost reduction.
EE Times has an exclusive video interview with Aart de Geus to talk about the AI-driven EDA, generative AI, talent, and the future of EDA.
Watch the video below:
Related Semiconductor IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
- TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
Related News
- EE Times - DAC special: Video interview with Synopsys CEO Aart De Geus
- Synopsys Announces Aart de Geus and Chi-Foon Chan to Become Co-CEOs
- Cadence and Google Collaborate to Scale AI-Driven Chip Design with ChipStack AI Super Agent on Google Cloud
- IP99: de Geus calls for core quality
Latest News
- First Benchmarks Revealed for Jalapeño, OpenAI’s Clean-Sheet General Purpose AI Accelerator ASIC
- MIPS Leads Open Standards Development for Physical AI Platforms as RISC-V International Premier Member
- SEALSQ’s Subsidiary IC'Alps Advances QASIC Roadmap for Sovereign, Quantum-Resistant Application-Specific Integrated Circuits
- NVMe 2.4 Update Adds Post-Quantum Security, Power Controls
- Agentrys Raises $24.5 Million to Build Agentic Design Automation for Chipmakers