Intel's 22-nm tri-gate SoC, how low can you leak?
Sylvie Barak, EETimes
12/10/2012 4:30 PM EST
The chip maker introduced a CPU version of its 22-nm offering in June, but Intel senior fellow Mark Bohr said in an interview that the recipe has been tweaked in order to scale down to a more mobile, ultra-low leakage version.
To read the full article, click here
Related Semiconductor IP
- DSP-Based 112G SerDes
- XTAL oscillator in TSMC-7nm
- GPU
- V-by-One Verification IP
- AI model compression IP
Related News
- Intel tips 22-nm tri-gate, but mobile is MIA
- Tabula Confirms Move to Intel's 22nm Process Featuring 3-D Tri-Gate Transistors
- Faraday Announces Plans to Develop Arm-based 64-core SoC on Intel 18A Technology
- Intel and Cadence Expand Partnership to Enable Best-in-Class SoC Design on Intel's Advanced Processes
Latest News
- Arteris Deployed by Speedata for Data Center Compute
- Siemens to acquire Defacto Technologies to complement its EDA portfolio with automated SoC design creation
- Mach42 Completes £7M Funding Round, Led by IP Group With Investment From BGF and Foresight Group
- ELECTRA IC Unveils Comprehensive IP Core Suite for Next-Generation Post-Quantum Cryptography
- CAST Enhances Serial Memory Controller IP with Encryption, Low-Power, and ASIL-Ready Options