Intel's 22-nm tri-gate SoC, how low can you leak?
Sylvie Barak, EETimes
12/10/2012 4:30 PM EST
SAN FRANCISCO -- Intel will describe its 22-nm tri-gate (FinFET) SoC technology for mobile applications Monday (Dec. 10) at the International Electron Devices Meeting (IEDM) here.
The chip maker introduced a CPU version of its 22-nm offering in June, but Intel senior fellow Mark Bohr said in an interview that the recipe has been tweaked in order to scale down to a more mobile, ultra-low leakage version.
To read the full article, click here
Related Semiconductor IP
- 100-10Gbps Ethernet MAC Controller
- SD Card Controller
- AXI4 Memory Controller IP Core
- AXI-Lite I2C Controller Core
- LVDS Transceiver IP core
Related News
- Intel tips 22-nm tri-gate, but mobile is MIA
- Tabula Confirms Move to Intel's 22nm Process Featuring 3-D Tri-Gate Transistors
- Faraday Announces Plans to Develop Arm-based 64-core SoC on Intel 18A Technology
- Intel and Cadence Expand Partnership to Enable Best-in-Class SoC Design on Intel's Advanced Processes
Latest News
- BrainChip Launches AKD1500 Raspberry Pi 5 Kit: Giving Developers a Direct Path from Prototype to Production
- Cadence Joins the Genesis Mission Consortium to Advance AI-Driven Scientific Discovery and Microelectronics Innovation
- Onsemi picks up Codasip’s low-end RISC-V business for $14.5 million
- Semidynamics and Nokia Explore Collaboration to Strengthen Europe’s Sovereign AI Capabilities
- VeriSilicon Introduces GLTiny™ 3D GPU Programming Model for Ultra-Low-Power, Memory-Efficient Wearable Devices