Ingot Systems Announces System Optimized PCI-Express x1 and x4 IP Cores
- Ingot Systems, the leading provider of ASIC Design Solutions in the form of niche IP, and services for Full Chip Design, Design Verification and Physical Design, today announced the availability of a system optimized PCI-Express x1 and x4 End Point IP Core. The IP7101 PCI-Express x1 IP Core and the IP7104 PCI-Express x4 IP Core are fully compliant with the PCI Express Base Specification v1.0a and v1.1, and are optimized for small die size, low-latency and very high payload bandwidth. Detailed product briefs are available on the Ingot Systems web site at www.ingotsys.com
Ingot PCI-Express End-Point Features- x1 and x4 versions
- Optimized for small die size and low power for cost sensitive applications
- Supports Low-latency communication to maximize payload bandwidth.
- Supports configurable packet sizes from 64B to 4 KB.
- Provides credit based flow control.
- Supports differentiated services using multiple virtual channels.
- Supports both PCI and native Hot-plug and Hot-Swap solutions.
- Supports Link-level data integrity.
- Supports PCI-level error handling and advance error reporting.
Ingot Systems is a premier ASIC design solutions company offering Design Solutions to customers in the form of Niche IP Solutions, Full-Chip Design, Design Verification and Physical Design Services. Our Niche IP Solutions include Video Encode/Decode, PCI-Express and Networking – all with advanced features that deliver high-performance in a minimum die area and with low power dissipation. Our design services utilize advanced and automated methodologies developed over years of doing successful ASIC designs. We use internally developed IP in the form of proven EDA tool flows, script based automation, extensive libraries of key functions to create our three main ASIC design solutions. Spec-2-IC is our Full-Chip ASIC design service, Robust-IC is our proven design verification process and Gate-2-IC is our automated platform for physical design.
Related Semiconductor IP
- High Channel Count DMA IP Core for PCI-Express
- Ultra Low-Latency IP PCI-express Framework
- Programmable PCIe2/SATA3 SERDES PHY on TSMC CLN28HPC
- Programmable Low Power SERDES on TSMC CLN40G
- Programmable Low Power SERDES on TSMC CLN28HPL
Related News
- Smartlogic Announces PCI Express Multichannel DMA IP Core optimized for Video Streaming
- PLD Applications' PCI-SIG-tested x1, x4, x8 PCI Express IP Core validated for FPGA and ASIC integration
- Lattice and Northwest Logic Deliver PCI Express X1, X4 and X8 Solutions
- Altera Delivers PCI-SIG Compliant x1 and x4 PCI Express Solution Supporting Arria GX FPGAs
Latest News
- Marvell, Microsoft and Oracle Establish OCP Working Group to Standardize Data Center Hardware Security
- At GAITA, PUFsecurity Shows How PUFrt and PUF-Based HSMs Give Agentic and Physical AI a Verifiable Root of Trust
- QuickLogic Secures Six-Figure eFPGA IP Contract for Automotive Industrial SoC
- Faraday Powers Intelligent Sensing with New 14nm MIPI C/D Combo PHY IP
- Cadence Wins Five 2026 TSMC OIP Partner of the Year Awards