GUC Tapes Out Complex 3D Stacked Die Design on Advanced FinFET Node Using Cadence Integrity 3D-IC Platform

January 10, 2024 -- Global Unichip Corporation (GUC), a leading global ASIC provider, has successfully taped out a complex 3D stacked die design on an advanced FinFET node process. The design, which involves a memory-on-logic configuration achieved with a wafer-on-wafer (WoW) structure using a flip-chip chip scale package, was created using the Cadence Integrity 3D-IC Platform. Seamless integration between the Cadence Integrity System Planner and Cadence Innovus Implementation System in the Integrity 3D-IC platform enabled the die-to-die interface planning and hierarchical die stacking in this complex design. This WoW design has been validated with first-pass silicon success.

The Integrity 3D-IC platform provides on-chip and off-chip analysis flows that enable cross-die timing, power planning, IR and thermal analysis, and seamless physical verification for the WoW 3D stack. To tape out this design, GUC used the Integrity 3D-IC platform with a specific focus on cross-die 3D planning and integrated analysis tools for system-level analysis. After planning, the 3D stacked die went through full implementation with the Innovus system. IR analysis was performed with the Voltus IC Power Integrity Solution, followed by early system-level LVS verification available through the Integrity 3D-IC platform.

“This tapeout of wafer-on-wafer stacked die design technology at advanced FinFET nodes is a big step towards realizing the full potential of true 3D-IC technology,” said Louis Lin, senior vice president of Design Services at GUC. “Using Cadence’s Integrity 3D-IC platform working seamlessly across all layers of a full 3D stack, we were able to implement a complex stacked die design on a flip-chip chip scale package using state-of-the-art techniques for cross-die partitioning, timing analysis, package layout, and analysis. The comprehensive nature of Cadence’s 3D-IC platform solution enabled us to handle the complexity and deliver an innovative multi-die stacked design on advanced FinFET nodes.”

Dr. Chin-Chi Teng, senior vice president and general manager in the Digital and Signoff Group at Cadence, said, “With the increase in demand for automation for multi-die solutions, it is necessary to provide a comprehensive solution for handling both the on-chip and off-chip complexity of a stacked die system. Cadence’s Integrity 3D-IC platform for unified 3D-IC design and analysis ties our best-in-class implementation technologies for SoC and package design with system-level planning and analysis. As the industry continues to move to different configurations of 3D stacked dies, the Integrity 3D-IC platform is a key enabler in achieving system-driven power, performance, and area through system technology co-optimization for next-generation 3D-IC designs.”

The automation and comprehensive nature of the Cadence Integrity 3D-IC platform solution enabled GUC to deliver an innovative multi-die stacked design on advanced FinFET nodes, laying the foundation for the development of next-generation 3D-IC designs.

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