Why Opt For Chip Stack, FD-SOI in Image Sensors?
Junko Yoshida, EETimes
1/28/2016 02:30 PM EST
MADISON, Wis. -- If Samsung’s latest smartphone TV commercial (which touts a number of superior camera features and ends with a tagline -- “It's Not a Phone, It's a Galaxy”) is any indication, the ingredient that matters most in smartphones today isn’t the phone. It’s the camera.
As camera functions become essential to differentiate embedded devices, designers of CMOS image sensors (CIS) find themselves wrestling with growing demands on multiple fronts – image quality, size of camera modules and overall cost.
Over the last few years, CIS vendors have embraced chip stacking. Under that option, a CIS is stacked with an image signal processor (ISP). As the next step, at least two major players, Sony and Samsung, are reportedly pondering the use of FD-SOI wafers in manufacturing ISPs for a chip stacked CIS.
To read the full article, click here
Related Semiconductor IP
- MIL-STD-1553 Controller IP
- UFS 5.x Device IP
- UCIe 3.x Controller IP
- Ethernet 800G PCS IP
- CHI to UCIe Bridge IP
Related News
- Sony To Use FD-SOI in Stacked Image Sensors
- CMOS Image Sensors See Higher Growth from Greater Diversity of Uses
- Sony Acquires Belgian Innovator of Range Image Sensor Technology, Softkinetic Systems S.A., in its Push Toward Next-Generation Range Image Sensors and Solutions
- CMOS Image Sensors Expected To Set Record-High Sales for Another Five Years
Latest News
- StarFive and LECARC Forge Partnership to Co-Develop RISC-V Server CPUs and Seize New Opportunities in the Agentic AI Era
- ASICLAND Selected as SK hynix’s Partner for Next-Gen eSSD Development, Establishing a ‘K-Semiconductor Win-Win’ Model
- onsemi to Acquire Synaptics to Enable the Next Generation of Intelligent Systems for Physical AI
- EdgeAI Licensed Andes Technology CPU IP to Power Next-Generation Edge AI Neuromorphic Solution
- Jim Keller: ‘AI Still Obeys the Old Laws of Compute’