Embedded FPGA to reach 65-nm in 2007, says M2000
Catherine Gross, EE Times
(10/31/2006 7:51 AM EST)
PARIS — Claiming to be already delivering the densest embedded FPGA (eFPGA) at the 90-nanometer manufacturing node, M2000 SA is in the process of preparing FPGA intellectual property targeting 65-nanometer designs. The first 65-nm tapeout is expected during the first half of 2007, the company said.
"What we are doing here is much more than a mere porting [the 90-nm design] as we are enhancing our cell structure, by adding hardwired operators," said Frederic Reblewski, chief executive officer of M2000 (Paris, France). This addition eliminates the need to program basic operators, such as adders, in the lookup tables and as a result, embedded functions execute much faster while using the same amount of silicon, he explained.
(10/31/2006 7:51 AM EST)
PARIS — Claiming to be already delivering the densest embedded FPGA (eFPGA) at the 90-nanometer manufacturing node, M2000 SA is in the process of preparing FPGA intellectual property targeting 65-nanometer designs. The first 65-nm tapeout is expected during the first half of 2007, the company said.
"What we are doing here is much more than a mere porting [the 90-nm design] as we are enhancing our cell structure, by adding hardwired operators," said Frederic Reblewski, chief executive officer of M2000 (Paris, France). This addition eliminates the need to program basic operators, such as adders, in the lookup tables and as a result, embedded functions execute much faster while using the same amount of silicon, he explained.
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