Efabless Corporation Launches Its Second AI-Generated Chip Design Contest
PALO ALTO, Calif., July 7, 2023 -- Efabless Corporation, the creator platform for chips, announces the launch of its second in a series of AI Generated Open-Source Silicon Design Challenges. In the first design challenge, several participants successfully submitted completed designs in just three weeks. The second challenge will extend the design time to two months to enable wider participation, more learnings, and more success. The challenge series is targeted at a broad range of participants including IC designers, university students, professors, industry experts, and even those who have never designed a chip.
A lot has been written about the rapid emergence of generative AI in chip design. Large Language Model (LLM) AI is widely acknowledged as being an important productivity tool, with questions raised about its limitations. The Efabless AI Generated Open-Source Silicon Design Challenge series engages a global community in LLM AI chip creation to demonstrate the state of the art over time. The use of open source and an open forum enables and encourages broad based sharing of solutions and experiences across the community, accelerating its development and adoption.
As with the first challenge in the series, contestants will use AI tools to generate Verilog code from natural language prompts, which they will then implement on the Efabless chipIgnite platform using the OpenLane open-source design flow.
The deadline for submissions is September 7, 2023. A panel of industry experts will select the top three designs and announce the winners on September 14, 2023. Efabless will once again fabricate the winning designs and award the winners packaged silicon devices incorporating their designs along with evaluation boards, amounting to a total value of $9,750.
"We are excited to launch the second AI Generated Open-Source Silicon Design Challenge," said Mike Wishart, CEO of Efabless. "Our inaugural contest showcased the incredible potential of AI in shaping the future of chip design, and we cannot wait to witness the exceptional ideas that will emerge this time around."
To learn more about the second AI Generated Open-Source Silicon Design Challenge, please visit https://efabless.com/ai-generated-design-contest-2
About Efabless
Efabless offers a platform applying open source and community models to enable a global community of chip experts and non-experts to collaboratively design, share, prototype and commercialize special purpose chips. Nearly 1000 designs and 450 tapeouts have been executed on Efabless over the past two years. The company’s customers include startups, universities, and research institutions around the world.
Related Semiconductor IP
- Band-Gap Voltage Reference with dual 2µA Current Source - X-FAB XT018
- 250nA-88μA Current Reference - X-FAB XT018-0.18μm BCD-on-SOI CMOS
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
- 16-Bit xSPI PSRAM PHY
Related News
- Efabless Reveals Winners of AI-Generated Silicon Design Challenge
- Speedata Raises $44M to Launch First-Ever Chip Designed Specifically for Accelerating Big Data Analytics - Compute's Second Largest Workload
- Synopsys and GlobalFoundries Establish Pilot Program to Bring Chip Design and Manufacturing to University Classrooms
- SmartSoC Solutions Partners with Cortus to Advance Chip Design and Manufacturing for SIM Cards, Smart Cards, Banking Cards, and E-Passports in India
Latest News
- SEMI Reports Worldwide Silicon Wafer Shipments Increase 13% Year-on-Year in Q1 2026
- POLYN Technology Announces Tapeout of Automotive Chip
- QuickLogic Establishes New Banking Relationship and Secures $10 Million Revolving Credit Facility
- TES is extending its PMU IP portfolio for X-FAB’s XT018 - 0.18µm BCD-on-SOI technology.
- RF Front-End Modules & Components IP Trends – Q1 2026 Monitoring Release