Dillon Engineering Releases Second Generation FFT IP Core

April 15, 2002 - Dillon Engineering today anounced the release of its FFT IP Core Version 2.0. The FFT IP Core is designed using ParaCore Architect ^TM which results in a core that can be tailored to meet the needs of any application. This IP Core is very well suited for any FPGA or ASIC device.

Some new features of the DE FFT IP Core V2.0 are:

• Integrated Hanning Window (user defined)
• Optional Magnitude Output
• Significant reductions is logic and memory usage
• Improved performance by up to 50%
• Increased accuracy with double width additions as part of complex multiplies
• Increased accuracy with true 1 + 0j and 0 + 1j twiddle factors

FFT IP Core Version 2.0 Datasheet. has been updated to include the FPGA logic requirements for various sizes and speeds of FFTs.

The FFT IP Core V2.0 is available for immediate delivery complete with test bench, support, HDL source, and targeted EDIF.

Current licensee's should contact DE IP Cores for upgrade details. Licensees on maintenance are entitled to the update at no charge.