CXL Update Emphasizes Security
By Gary Hilson, EETImes (January 3, 2025)
The latest point release to the Compute Express Link specification aims to optimize monitoring and management and enhance functionality for operating systems and applications—all while extending security.
The updates reflect the rapid growth of AI in the data center, even though the coherent connectivity protocol was conceived before the AI boom took off, Anil Godbole, CXL Consortium marketing working group co-chair, said in a briefing with EE Times.
The latest CXL update, CXL 3.2, adds several monitoring and management capabilities, including a CXL hot-page monitoring unit (CHMU) for memory tiering, common event record, compatibility with PCIe management message pass through (MMPT) and CXL online firmware (FW) activation.
To read the full article, click here
Related Semiconductor IP
- CXL 4 Verification IP
- VIP for Compute Express Link (CXL)
- CXL 3.0 Controller
- CXL Controller
- CXL 4.0/3.2/3/2 Verification IP
Related News
- Key Industry Players Converge to Advance CXL, a New High-Speed CPU Interconnect for Breakthrough Data Center Performance
- SmartDV Speeds Delivery of its New CXL Verification IP
- Synopsys Delivers Industry's First Compute Express Link (CXL) IP Solution for Breakthrough Performance in Data-Intensive SoCs
- Compute Express Link Consortium (CXL) Officially Incorporates; Announces Expanded Board of Directors
Latest News
- Akeana Collaborates with Samsung Electronics, fast-tracking RISC-V Customers, Ecosystem for Server and Agentic AI Silicon
- Arteris Technology Licensed by SiEngine for Next – Generation Automotive SoCs
- Innatera and Akeana collaborate to advance energy-efficient RISC-V compute for edge AI
- SOC-E and SafeCore Devices to unveil a new TSN End Point IP Core: AeroTSN-EP
- RISC-V Market Leadership Helped Andes Technology Drive Cumulative Shipments of AndesCore-Powered™ SoCs Beyond the 20 Billion Mark