CXL Put Through Its Paces

By Gary Hilson, EETimes (December 10, 2021)

The Compute Express Link (CXL) has evolved to the point where the pipeline of enabling technologies is emerging.

The recent SC21 supercomputing conference provided an opportunity for several vendors to demonstrate their contributions to the growing CXL ecosystem, with technologies spanning controllers, testing and validation and memories.

As CXL’s value proposition focuses on making disaggregated resources including memory available on demand for a given workload, another focus is composability, a capability frequently associated with heterogeneous computing.

For example, endpoint controller IP from Cadence Design Systems emerged as the CXL specification was taking shape, said Gopi Krishnamurthy, a Cadence architect for PCIe and CXL. “A major challenge in developing this IP while the specification was still evolving in 2020 was the lack of CXL 2.0 host platform availability for [interoperability] testing.” Cadence partnered with Intel to simulate testing with future processor designs that implement CXL support. “Through simulation, Intel could ensure backward compatibility against its existing CXL 1.1 solutions,” Krishnamurthy said.

The interoperability simulation involved dropping the Cadence CXL endpoint’s register transfer level into Intel’s RTL simulation environment, replacing the endpoint bus functional model. The partners then developed a joint test plan that included use cases and traffic patterns for CXL 1.1/2.0 link training and discovery, CXL.mem, CXL.cache and mixed CXL.mem/CXL.cache traffic.

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