Creonic GmbH joins NewSpace Initiative
Kaiserslautern, Germany -- May 10, 2022 – Creonic GmbH recently joined the NewSpace Initiative launched by the BDI (Bundesverband der Deutschen Industrie). BDI is a network of German companies that are active in the NewSpace segment.
About the NewSpace Initiative
Private companies in the German space sector have joined forces in the NewSpace Initiative. Innovations in space travel are increasingly in the hands of private companies. This circumstance is revolutionizing a sector in which, for a long time, only states and their space agencies were active. The commercialization of space travel is also a huge opportunity for German companies. NewSpace can democratize access to space technologies by, among other things, enabling participating companies to provide data for the necessary digital services from space. To bundle competencies and create synergies, the BDI has launched the NewSpace Initiative. It sends a strong signal to the German and European space industry: We are on the move together and are driving space innovations forward.
About Creonic GmbH
Creonic GmbH is based in Kaiserslautern, Germany, develops microchips, components and algorithms for modems, data centers and satellites. In the information age, such elements are becoming increasingly important. Creonic specializes in storing and transporting enormous amounts of data. Today, transmission is often satellite-based, which is where Creonic’s products are used. With Creonic’s chip designs, companies from start-ups to global corporations can develop their infrastructure.
For more information please visit our website at www.creonic.com.
Related Semiconductor IP
- AXI to UCIe FDI Interface IP
- 45SPCLO UCIe-Class 1-32Gbps Low Power Receiver IP (NRZ)
- 45SPCLO UCIe-Class 1-32Gbps Low Power Transmitter IP (NRZ)
- Peripheral Sensor Interface (PSI5) Host Controller
- Link Acceleration Unit
Related News
- Creonic Starts Wideband Satellite Initiative with Launch of New DVB-S2X IP Cores
- Open SystemC Initiative Advances IP Interoperability and Reuse with New Draft Standard for Transaction-Level Modeling
- Moortec Announce route2IP - a Collaborative Initiative for Sub-Picosecond Jitter PLL Design
- Imperas Unleashes Open Source Initiative to Establish Common, Open Standard for Multicore SoC Design
Latest News
- onsemi to Acquire Synaptics to Enable the Next Generation of Intelligent Systems for Physical AI
- EdgeAI Licensed Andes Technology CPU IP to Power Next-Generation Edge AI Neuromorphic Solution
- Jim Keller: ‘AI Still Obeys the Old Laws of Compute’
- OpenAI and Broadcom unveil LLM-optimized inference chip
- RAAAM Selects Avnet ASIC as its VCA Partner for TSMC’s 2nm GCRAM Development and Qualification