Confab wants mainstream recruits for SoC design

Confab wants mainstream recruits for SoC design
By Michael Santarini, EE Times
February 27, 2001 (1:22 p.m. EST)
URL: http://www.eetimes.com/story/OEG20010226S0012

The Intellectual Property/System-on-Chip 2001 conference, set for March 19-23 in Santa Clara, Calif., has education on its mind. The successor to last year's IP2000 conference hinges on a three-day educational program ranging from two-hour classes to full-day tutorials, all geared to bring system-on-chip (SoC) design techniques to "mainstream" designers, said conference chair Ron Wilson, the publisher of Integrated System Design magazine.

IP/SoC 2001 was developed by CMP Media, EE Times' parent company, and is sponsored by EE Times and Integrated System Design. It's co-located with the PCB Design Conference West, which was also created by CMP Media.

Joe Pumo, director of Motorola Inc.'s system-on-chip design technology group, will offer a from-the-trenches view of SoC design in his keynote on Wednesday, March 21. Pumo will discuss some of the challenges that his team has encountered when confronted with tough SoC designs.

Full-da y tutorials on Monday and Friday will provide overviews of SoC verification techniques, hardware design using C/C++ and platform-based design for SoC; and of SystemC for SoC design, the Rosetta system-level specification language, and future technologies and markets for programmable platform-based design, respectively.

The conference's educational program has three tracks: success factors in SoC design, SoC verification and platform-based design. The success-factors track includes classes on system-level co-design, intellectual-property authoring and integration, choosing the right architecture, IP evaluation, analog IP, whole-chip design, simulation model accuracy and hardware/software integration. A panel moderated by Steve Schulz, organizer of the success-factors track, will probe the IP business model for embedded SoC design. The verification track includes classes in design-for-test techniques, developing an SoC verification plan, mixed-signal design, signal integrity, verification reuse, IP rat ing, equivalence checking for memories and high-level languages for SoC verification.

The platform-based design track includes classes in user-configurable ARC microprocessor cores, the Trimedia VLIW architecture, the Tensilica configurable microprocessor, the Actel embeddable core, the Palmchip interconnect infrastructure, the Sonics network, the Triscend configurable platform and Morphics Technology.

Instructors will include Janick Bergeron, moderator of the online Verification Guild newsletter; Mike Baird, president of Willamette HDL; Kurt Keutzer, professor of electrical engineering and computer science at the University of California at Berkeley; Yatin Trivedi, director of engineering at Intrinsix; and Pierre Bricaud, director of marketing for Mentor Graphics' Inventra Division.

A business forum planned for Monday, March 19, will include a user panel titled "IP Build vs. Buy" and a speech by Eric Chen, senior analyst at J.P. Morgan, on "Rethinking Semiconductor Intellectual Prop erty." Registration is separate for this event. The exhibit floor, which will be open Tuesday through Thursday, will feature more than 50 IP, EDA and platform-based SoC companies. Registration and further information can be found at www.ipshows.com. Information about PCB West is at www.pcbshows.com.