CEO interview: Coby Hanoch, Weebit Nano on ReRAM for AI
By Nick Flaherty, eeNews Europe (August 13, 2024)
But now the development of in memory computing and neuromorphic AI architecture is driving significantly higher demand for memory on leading edge process technologies, Coby Hanoch, CEO of Weebit Nano tells Nick Flaherty of eeNews Europe.
One technology proposed for next generation microcontrollers is resistive RAM (ReRAM), which for Weebit has been in development for nearly a decade using technology from French research lab CEA-Leti.
To read the full article, click here
Related Semiconductor IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
- TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
Related News
- Weebit Nano and Silvaco Form Development Program Partnership to Create ReRAM Models and Design Tools
- Weebit Nano and Silvaco Develop New Simulation Capabilities to Increase ReRAM Adoption
- Weebit Nano continues ReRAM innovation: Files new patents optimising programming of ReRAM
- Weebit Nano successfully demonstrates integration of selector with ReRAM cell for the stand-alone memory market
Latest News
- First Benchmarks Revealed for Jalapeño, OpenAI’s Clean-Sheet General Purpose AI Accelerator ASIC
- MIPS Leads Open Standards Development for Physical AI Platforms as RISC-V International Premier Member
- SEALSQ’s Subsidiary IC'Alps Advances QASIC Roadmap for Sovereign, Quantum-Resistant Application-Specific Integrated Circuits
- NVMe 2.4 Update Adds Post-Quantum Security, Power Controls
- Agentrys Raises $24.5 Million to Build Agentic Design Automation for Chipmakers